View TDA9898HL_4135633.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA9897; TDA9898
Multistandard hybrid IF processing
Rev. 03 -- 11 January 2008 Product data sheet
1. General description
The Integrated Circuit (IC) is suitable for Intermediate Frequency (IF) processing including global multistandard Analog TV (ATV), Digital Video Broadcast (DVB) and mono FM radio using only 1 IC and 1 to 3 fixed Surface Acoustic Waves (SAWs) (application dependent). TDA9898 including L and L-accent standard. TDA9897 without L and L-accent standard.
2. Features
2.1 General
I I I I I 5 V supply voltage I2C-bus control over all functions Four I2C-bus addresses provided; selection by programmable Module Address (MAD) Three I2C-bus voltage level supported; selection via pin BVS Separate gain controlled amplifiers with input selector and conversion for incoming IF [analog Vision IF (VIF) or Sound IF (SIF) or Digital TV (DTV)] allows the use of different filter shapes and bandwidths All conventional ATV standards applicable by using DTV bandwidth window [Band-Pass (BP)] filter Easy to use default settings for almost every standard provided, selectable via I2C-bus Two 4 MHz reference frequency stages; the first one operates as crystal oscillator, the second one as external signal input Stabilizer circuit for ripple rejection and to achieve constant output signals Smallest size, simplest application ElectroStatic Discharge (ESD) protection for all pins
I I I I I I
2.2 Analog TV processing
I Gain controlled wide-band VIF amplifier; AC-coupled I Multistandard true synchronous demodulation with active carrier regeneration: very linear demodulation, good intermodulation figures, reduced harmonics and excellent pulse response I Internal Nyquist slope processing; switch-off able for alternative use of inexpensive Nyquist slope SAW filter with additive video noise improvement I Gated phase detector for L and L-accent standards I Fully integrated VIF Voltage-Controlled Oscillator (VCO), alignment-free, frequencies switchable for all negative and positive modulated standards via I2C-bus I VIF Automatic Gain Control (AGC) detector for gain control; operating as a peak sync detector for negative modulated signals and as a peak white detector for positive modulated signals
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
I Optimized AGC modes for negative modulation; e.g. very fast reaction time for VIF and SIF I Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit Digital-to-Analog Converter (DAC); AFC bits can be read-out via I2C-bus I High precise Tuner AGC (TAGC) TakeOver Point (TOP) for negative modulated standards; TOP adjust via I2C-bus I TAGC TOP for positive standards and Received Signal Strength Indication (RSSI); adjustable via I2C-bus or alternatively by potentiometer I Fully integrated Sound Carrier (SC) trap for any ATV standard (SC at 4.5 MHz, 5.5 MHz, 6.0 MHz and 6.5 MHz) I SIF AGC for gain controlled SIF amplifier and high-performance single-reference Quasi Split Sound (QSS) mixer I Fully integrated sound BP filter supporting any ATV standard I Optional use of external FM sound BP filter I AM sound demodulation for L and L-accent standard I Alignment-free selective FM Phase-Locked Loop (PLL) demodulator with high linearity and low noise; external FM input I VIF AGC voltage monitor output or port function I VIF AFC current or tuner, SIF or FM AGC voltage monitor output I 2nd SIF output, gain controlled by internal SIF AGC or by internal FM carrier AGC for Digital Signal Processor (DSP) I Fully integrated BP filter for 2nd SIF at 4.5 MHz, 5.5 MHz, 6.0 MHz or 6.5 MHz
2.3 Digital TV processing
I I I I I I I I I I I I I Applicable for terrestrial and cable TV reception 70 dB variable gain wide-band IF amplifier (AC-coupled) Gain control via external control voltage (0 V to 3 V) 2 V (p-p) differential low IF (downconverted) output or 1 V (p-p) 1st IF output for direct Analog-to-Digital Converter (ADC) interfacing DVB downconversion with integrated selectivity for Low IF (LIF)/Zero IF (ZIF) Integrated anti-aliasing tracking low-pass filter Fully integrated synthesizer controlled oscillator with excellent phase noise performance Synthesizer frequencies for a wide range of world wide DVB standards (for IF center frequencies of 34.5 MHz, 36 MHz, 44 MHz and 57 MHz) All DVB bandwidth ranges supported (including ZIF I/Q) TAGC detector for independent tuner gain control loop applications TAGC operating as peak detector, fast reaction time due to additional speed-up detector Port function TAGC voltage monitor output
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
2 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
2.4 Dual mode
I Fully performed DTV processing and additional ATV video signal processing in parallel, but with reduced performance, for very fast channel scan I VIF AGC voltage monitor output or port function I VIF AFC current monitor output or TAGC voltage output
2.5 FM radio mode
I Gain controlled wide-band Radio IF (RIF) amplifier; AC-coupled I Buffered RIF amplifier wide-band output, gain controlled by internal RIF AGC I Fully integrated BP filter for 2nd RIF at 4.5 MHz, 5.5 MHz, 6.0 MHz, 6.5 MHz or 10.7 MHz I 2nd RIF output, gain controlled by internal RIF AGC or by internal FM carrier AGC for DSP I Alignment-free selective FM PLL demodulator with high linearity and low noise I Precise fully digital AFC detector with 4-bit DAC; AFC bits read-out via I2C-bus I Port function I Radio AFC current or tuner, RIF or FM AGC voltage monitor output
3. Applications
I Analog and digital TV front-end applications for TV sets, recording applications and personal computer cards
4. Quick reference data
Table 1. Quick reference data VP = 5 V; Tamb = 25 C. Symbol VP IP Video part Vi(IF)(RMS) GVIF(cr) fVIF fVIF(dah) RMS IF input voltage control range VIF gain VIF frequency digital acquisition help VIF frequency window see Table 25 related to fVIF all standards except M/N M/N standard Vo(video)(p-p) peak-to-peak video output voltage see Figure 10 positive or negative modulation; normal mode and sound carrier on trap bypass mode and sound carrier off
TDA9897_TDA9898_3
Parameter supply voltage supply current
Conditions
[1]
Min 4.5 -
Typ 5.0 -
Max 5.5 190
Unit V mA
Analog TV signal processing lower limit at -1 dB video output signal 60 [2]
60 66 2.3 1.8 2.0
100 2.3
V dB MHz MHz MHz V
1.7
[3]
-
1.1
-
V
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
3 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 1. Quick reference data ...continued VP = 5 V; Tamb = 25 C. Symbol Gdif Parameter differential gain Conditions Min
[2][4]
Typ 2 2 8
Max 5 7 4 4 -
Unit % % deg deg MHz
"ITU-T J.63 line 330"
B/G standard L standard
[2][4]
dif
differential phase
"ITU-T J.63 line 330"
B/G standard L standard
[3]
Bvideo(-3dB)
-3 dB video bandwidth
trap bypass mode and sound carrier off; AC load: CL < 20 pF, RL > 1 k M/N standard; f = fSC1 = 4.5 MHz; see Figure 21 B/G standard; f = fSC1 = 5.5 MHz; see Figure 23
6
SC1
first sound carrier attenuation
[3]
38
-
-
dB
[3]
35
-
-
dB
(S/N)w
weighted signal-to-noise ratio
normal mode and sound carrier on; B/G standard; 50 % grey video signal; unified weighting filter ("ITU-T J.61"); see Figure 20 normal mode and sound carrier on; fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 11 AFC TV mode
[2][5]
53
57
-
dB
PSRRCVBS
power supply ripple rejection on pin CVBS
[2]
14
20
-
dB
IAFC/fVIF Audio part Vo(AF)(RMS)
change of AFC current with VIF frequency RMS AF output voltage
[6]
0.85
1.05
1.25
A/kHz
FM: QSS mode; 27 kHz FM deviation; 50 s de-emphasis AM: 54 % modulation FM: 50 s de-emphasis; FM deviation: for TV mode 27 kHz and for radio mode 22.5 kHz AM: 54 % modulation; BP on; see Figure 33
430
540
650
mV
400 -
500 0.15
600 0.50
mV %
THD
total harmonic distortion
80
0.5 100
1.0 -
% kHz
f-3dB(AF)
AF cut-off frequency
W3[2] = 0; W3[4] = 0; without de-emphasis; FM window width = 237.5 kHz
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
4 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 1. Quick reference data ...continued VP = 5 V; Tamb = 25 C. Symbol (S/N)w(AF) Parameter AF weighted signal-to-noise ratio Conditions Min 48 Typ 56 Max Unit dB
"ITU-R BS.468-4"
FM: 27 kHz FM deviation; 50 s de-emphasis; vision carrier unmodulated; FM PLL only AM: BP off
44 14 90 45
50 20 140 70
180 90
dB dB mV mV
PSRR Vo(RMS)
power supply ripple rejection RMS output voltage
fripple = 70 Hz; see Figure 11 IF intercarrier single-ended to GND; SC1 on; SC2 off IF intercarrier single-ended to GND; L standard; without modulation; BP on; W7[5] = 0
FM sound part
Vi(FM)(RMS) RMS FM input voltage gain controlled operation; W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01; see Figure 15 AFC radio mode referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 %
[6]
2
-
300
mV
IAFC/fRIF AM
change of AFC current with RIF frequency AM suppression
0.85 35
1.05 46
1.25 -
A/kHz dB
Digital TV signal processing Digital direct IF Vo(dif)(p-p) peak-to-peak differential output voltage between pin OUT2A and pin OUT2B W4[7] = 0 W4[7] = 1 GIF(max) GIF(cr) PSRR maximum IF gain control range IF gain power supply ripple rejection residual spurious at nominal differential output voltage dependent on power supply ripple fripple = 70 Hz fripple = 20 kHz Digital low IF Vo(dif)(p-p) GIF(max) GIF(cr) fsynth
TDA9897_TDA9898_3
[7]
[8]
1.0 0.50 83 66
1.1 0.55 -
V V dB dB
output peak-to-peak level to input RMS level ratio
60
[8] [8]
[7]
60 60 2 89 66 -
-
dB dB V dB dB MHz
peak-to-peak differential output voltage maximum IF gain control range IF gain synthesizer frequency
between pin OUT1A and pin OUT1B; W4[7] = 0 output peak-to-peak level to input RMS level ratio see Table 35 and Table 36
60 -
[8]
[8]
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
5 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 1. Quick reference data ...continued VP = 5 V; Tamb = 25 C. Symbol n(synth) Parameter synthesizer phase noise Conditions with 4 MHz crystal oscillator reference; fsynth = 31 MHz; fIF = 36 MHz at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz ripple(pb)LIF low IF pass-band ripple 6 MHz bandwidth 7 MHz bandwidth 8 MHz bandwidth stpb image C/N stop-band attenuation image rejection carrier-to-noise ratio 8 MHz band; f = 15.75 MHz -10 MHz to 0 MHz; BP on at fo = 4.9 MHz; Vi(IF) = 10 mV (RMS); see Figure 37 between pin OUT1A and pin OUT1B or between pin OUT2A and pin OUT2B; W4[7] = 0 output peak-to-peak level to input RMS level ratio see Table 35 and Table 36 with 4 MHz crystal oscillator reference; fsynth = 31 MHz; fIF = 36 MHz at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz Reference frequency input from external source fref Vref(RMS) reference frequency RMS reference voltage W7[7] = 0 W7[7] = 0; see Figure 34 and Figure 46
[11] [8] [8] [8] [8] [8][9][10] [8] [8] [8] [8]
Min
Typ
Max
Unit
89 89 98 115 30 30 112
99 99 102 119 40 34 118
2.7 2.7 2.7 -
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dB dB dB dB dB dBc/Hz
Digital zero IF Vo(dif)(p-p) peak-to-peak differential output voltage
[7]
-
2
-
V
GIF(max) GIF(cr) fsynth n(synth)
maximum IF gain control range IF gain synthesizer frequency synthesizer phase noise
[8]
60 -
89 66 -
-
dB dB MHz
[8]
89 89 98 115 15
99 99 102 119 4 150
500
dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz mV
[1] [2] [3] [4] [5] [6]
Values of video and sound parameters can be decreased at VP = 4.5 V. AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps. The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 24. In this way the full composite video spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p). Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps. Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter ("ITU-T J.64"). To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The AFC steepness can be changed by resistors R1 and R2.
(c) NXP B.V. 2008. All rights reserved.
TDA9897_TDA9898_3
Product data sheet
Rev. 03 -- 11 January 2008
6 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
[7] [8] [9]
With single-ended load for fIF < 45 MHz RL 1 k and CL 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 k and CL 3 pF to ground. This parameter is not tested during production and is only given as application information. Noise level is measured without input signal but AGC adjusted corresponding to the given input level.
[10] Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off. [11] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum FM deviation, sound trap frequency, LIF band-pass cut-off frequency and ZIF low-pass cut-off frequency as well as the accuracy of the synthesizer.
5. Ordering information
Table 2. Ordering information Package Name TDA9897HL/V2/S1 LQFP48 TDA9897HN/V2 HVQFN48 Description plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm Version SOT313-2 SOT619-1 SOT313-2 SOT619-1 Type number
TDA9898HL/V2/S1 LQFP48 TDA9898HN/V2 HVQFN48
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
7 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
6. Block diagram
SDA 23
SCL 24
i.c. 14 I2C-BUS
ADRSEL BVS 25 32
GNDD 22 LFSYN2 1 SYNTHESIZER AND VCO
A
TDA9898
AGCDIN 36 SIF AGC
AM average FM peak
B
IF3A IF3B
3 4
sideband Q I SIDEBAND FILTER D C
IF1A IF1B
6 7 2x VIF AGC sideband (L-accent) I Q 10 5 45 DECODER I2C-BUS TOPNEG VIF AFC SOUND CARRIER TRAP GROUP DELAY EQUALIZER NYQUIST FILTER E
IF2A IF2B CIFAGC
9
i.c.
VIF PLL AND ACQUISITION HELP
F
trap reference SYNTHESIZER AND VCO standard
PEAK AGC TUNER 47
TAGC
RSSI DETECTOR AND L STANDARD TUNER AGC
I2C-BUS TOP2 AND RSSI
G H
48 GND
2, 18, 37
8 CTAGC
11 TOP2 optional tuner AGC TOP for positive modulation and radio signal strength detector onset
13 LFVIF
38 LFSYN1
n.c.
008aaa090
Fig 1. Block diagram of TDA9898 (continued in Figure 2)
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
8 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
4 MHz reference input R(2) EXTERNAL SOUND BAND-PASS FILTER(1) VP 43, 44 SUPPLY +3 dB GNDA 40, 41 EXTFILO 15 EXTFILI 17 FREF 46 4 MHz FREQUENCY REFERENCE
R(2)
OPTXTAL 39
A B 29 30 BP on/off C BAND-PASS FILTER D 21 34 CAF2 20 CDEEM E FM SWITCH FM AMPLIFIER FM CARRIER AGC AM F AM DEMODULATOR FM AND FM NARROW-BAND PLL AM 16 TAGC SIF AGC FM AGC AFC 33 G H VIF AGC I2C-bus 35, 42 19 LFFM n.c. port 12 MPP1 MPP2 31 28 CAF1 AUD OUTPUT SWITCH
TDA9898
OUT2A OUT2B
26 27
OUT1A OUT1B
EXTFMI
CVBS
008aaa055
(1) Optional. (2) Connect resistor if input or crystal is not used.
Fig 2. Block diagram of TDA9898 (continued from Figure 1)
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
9 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
SDA 23
SCL 24
i.c. 14 I2C-BUS
ADRSEL BVS 25 32
GNDD 22 LFSYN2 1 SYNTHESIZER AND VCO
A
TDA9897
AGCDIN 36 SIF AGC FM peak
IF3A IF3B
3 4
sideband Q I SIDEBAND FILTER C B
IF1A IF1B
6 7 2x VIF AGC sideband I Q 10 NYQUIST FILTER D
IF2A IF2B
9
DECODER i.c. 45
I2C-BUS TOPNEG
VIF PLL AND ACQUISITION HELP
VIF AFC
SOUND CARRIER TRAP
GROUP DELAY EQUALIZER
E
trap reference SYNTHESIZER AND VCO standard
PEAK AGC TUNER 47
TAGC
RSSI DETECTOR AND IF BASED TUNER AGC
I2C-BUS TOP2 AND RSSI
F G
48 GND
2, 5, 18, 37
8 CTAGC
n.c.
11 TOP2 optional tuner AGC TOP for IF based tuner AGC and radio signal strength detector onset
13 LFVIF
38 LFSYN1
008aaa091
Fig 3. Block diagram of TDA9897 (continued in Figure 4)
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
10 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
4 MHz reference input R(2) EXTERNAL SOUND BAND-PASS FILTER(1) VP 43, 44 SUPPLY +3 dB GNDA 40, 41 EXTFILO 15 EXTFILI 17 FREF 46 4 MHz FREQUENCY REFERENCE
R(2)
OPTXTAL 39
A 29 30 BP on/off B BAND-PASS FILTER C 21 34 CAF2 20 CDEEM D FM SWITCH FM AMPLIFIER FM CARRIER AGC 31 28 CAF1 AUD OUTPUT SWITCH
TDA9897
OUT2A OUT2B
26 27
OUT1A OUT1B
EXTFMI
E
DEMODULATOR FM AND FM NARROW-BAND PLL
16 TAGC SIF AGC FM AGC AFC 33
MPP2
CVBS
F G VIF AGC I2C-bus 35, 42 19 LFFM n.c. port 12 MPP1
008aaa056
(1) Optional. (2) Connect resistor if input or crystal is not used.
Fig 4. Block diagram of TDA9897 (continued from Figure 3)
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
11 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
7. Pinning information
7.1 Pinning
39 OPTXTAL
38 LFSYN1
41 GNDA
40 GNDA
47 TAGC
46 FREF
48 GND
LFSYN2 n.c. IF3A IF3B CIFAGC(1) IF1A IF1B CTAGC IF2A
1 2 3 4 5 6 7 8 9
37 n.c. 36 AGCDIN 35 n.c. 34 CAF2 33 CVBS 32 BVS 31 AUD 30 OUT2B 29 OUT2A 28 CAF1 27 OUT1B 26 OUT1A 25 ADRSEL SCL 24
008aaa040
TDA9897HL TDA9898HL
IF2B 10 TOP2 11 MPP1 12 LFVIF 13 i.c. 14 EXTFILO 15 MPP2 16 EXTFILI 17 n.c. 18 LFFM 19 CDEEM 20 EXTFMI 21 GNDD 22 SDA 23
(1) Not connected for TDA9897HL.
Fig 5. Pin configuration for LQFP48
TDA9897_TDA9898_3
42 n.c.
45 i.c.
44 VP 43 VP
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
12 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
39 OPTXTAL
38 LFSYN1
41 GNDA
40 GNDA
47 TAGC
46 FREF
48 GND
42 n.c.
45 i.c.
44 VP
LFSYN2 n.c. IF3A IF3B CIFAGC(1) IF1A IF1B CTAGC IF2A
1 2 3 4 5 6 7 8 9
43 VP
terminal 1 index area
37 n.c. 36 AGCDIN 35 n.c. 34 CAF2 33 CVBS 32 BVS 31 AUD 30 OUT2B 29 OUT2A 28 CAF1 27 OUT1B 26 OUT1A 25 ADRSEL SCL 24
008aaa041
TDA9897HN TDA9898HN
IF2B 10 TOP2 11 MPP1 12 LFVIF 13 i.c. 14 EXTFILO 15 MPP2 16 EXTFILI 17 n.c. 18 LFFM 19 CDEEM 20 EXTFMI 21 GNDD 22 SDA 23
Transparent top view
(1) Not connected for TDA9897HN.
Fig 6. Pin configuration for HVQFN48
7.2 Pin description
Table 3. Symbol LFSYN2 n.c. IF3A IF3B CIFAGC IF1A IF1B CTAGC IF2A IF2B TOP2 MPP1 LFVIF i.c. EXTFILO Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TOP potentiometer for positive modulated standards and RSSI reference multipurpose pin 1: VIF AGC monitor output or port function loop filter VIF PLL internally connected; connect to ground output to external filter TAGC capacitor IF symmetrical input 2 for vision or digital TDA9898: IF AGC capacitor; L standard TDA9897: not connected IF symmetrical input 1 for vision or digital Description loop filter synthesizer 2 (conversion synthesizer) not connected IF symmetrical input 3 for sound
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
13 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Pin description ...continued Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 audio signal output I2C-bus voltage select composite video signal output DC decoupling capacitor 2 not connected AGC input for DIF amplifier for e.g. input from channel decoder AGC not connected loop filter synthesizer 1 (filter control synthesizer) optional quartz input analog ground analog ground not connected supply voltage supply voltage internally connected; connect to ground 4 MHz reference input TAGC output ground; plateau connection Direct Current (DC) decoupling capacitor 1 zero IF Q or 1st Digital IF (DIF) symmetrical output Description multipurpose pin 2: SIF AGC or FM AGC or TAGC or VIF AFC or FM AFC monitor output input from external filter not connected loop filter FM PLL de-emphasis capacitor external FM input digital ground I2C-bus data input and output I2C-bus clock input address select zero IF I or low IF or 2nd sound intercarrier symmetrical output
Table 3. Symbol MPP2 EXTFILI n.c. LFFM CDEEM EXTFMI GNDD SDA SCL ADRSEL OUT1A OUT1B CAF1 OUT2A OUT2B AUD BVS CVBS CAF2 n.c. AGCDIN n.c. LFSYN1 OPTXTAL GNDA GNDA n.c. VP VP i.c. FREF TAGC GND
8. Functional description
8.1 IF input switch
Different signal bandwidth can be handled by using two signal processing chains with individual gain control.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
14 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Switch configuration allows independent selection of filter for analog VIF and for analog SIF (used at same time) or DIF. The switch takes into account correct signal selection for TAGC in the event of VIF and DIF signal processing.
8.2 VIF demodulator
ATV demodulation using 6 MHz DVB window (band-pass) filter (for 6 MHz, 7 MHz or 8 MHz channel width). IF frequencies adapted to enable the use of different filter configurations. The Nyquist processing is integrated. For optional use of standard Nyquist filter the integrated Nyquist processing can be switched off. Sideband switch supplies selection of lower or upper sideband (e.g. for L-accent). Equalizer provides optimum pulse response at different standards [e.g. to cope with higher demands for Liquid Crystal Display (LCD) TV]. Integrated sound traps. Sound trap reference independent from received 2nd sound IF (reference taken from integrated reference synthesizer). IF level selection provides an optimum adaptation of the demodulator to high linearity or low noise.
8.3 VIF AGC and tuner AGC
8.3.1 Mode selection of VIF AGC
Peak white AGC for positive modulation mode with adaptation for speed up and black level AGC (using proven system from TDA9886). For negative modulation mode equal response times for increasing or decreasing input level (optimum for amplitude fading) or normal peak AGC or ultra fast peak AGC.
8.3.2 VIF AGC monitor
VIF AGC DC voltage monitor output (with expanded internal characteristic). VIF AGC read out via I2C-bus (for IF level indication) with zero-calibration via TOP setting (TOP setting either via I2C-bus or via TOP potentiometer).
8.3.3 Tuner AGC
Independent integral tuner gain control loop (not nested with VIF AGC). Integral characteristic provides high control accuracy. Accurate setting of tuner control onset (TOP) for integral tuner gain control loop via I2C-bus. For L standard, TAGC remains VIF AGC nested, as from field experience in the past this narrow-band TAGC gives best performance.
TDA9897_TDA9898_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
15 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Thus two switchable TAGC systems for negative/DIF and positive modulation implemented. L standard TAGC output changed from current output to voltage output, as it is not necessary to adapt for other than 5 V tuner. L standard tuner time constant switching integrated (= speed up function in the event of step into high input levels), to minimize external application. For high TOP accuracy at L standard, additional adjustment via optional potentiometer or I2C-bus is provided. Tuner AGC status bit provided. This function enables TOP alignment without need for TAGC voltage measurement (e.g. for TOP alignment in a complete set, where access to internal signals is not possible).
8.4 DIF/SIF FM and AM sound AGC
External AGC control input for DIF. DIF includes 1st IF, zero IF and low IF. Integrated gain control loop for SIF. Bandwidth of AGC control for FM SIF related to used SAW bandwidth. Peak AGC control in the event of FM SIF. Ultra fast SIF AGC time constant when VIF AGC set to ultra fast mode. Slow average AGC control in the event of AM sound. AM sound AGC related to AM sound carrier level. Fast AM sound AGC in the event of fast VIF AGC (speed up). SIF AGC DC voltage monitor output with expanded internal characteristic.
8.5 Frequency phase-locked loop for VIF
Basic function as previous TDA9887 design. PLL gating mode for positive and negative modulation, optional. PLL optimized for either overmodulation or strong multipath.
8.6 DIF/SIF converter stage
Frequency conversion with sideband suppression. Selection mode of upper or lower sideband for pass or suppression. Suppression around zero for frequency conversion. I/Q output mode for zero IF conversion. Conversion mode selection via synthesizer for DIF and radio mode or via VIF Frequency Phase-Locked Loop (FPLL) for TV QSS sound (FM/AM).
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
16 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
External BP filter (e.g. for 4.5 MHz) for additional filtering, optional. Bypass mode selection for use of external filter. Integrated SIF BP tracking filter for chroma suppression. Integrated tracking filters for LIF and ZIF. Symmetrical output stages for DIF, ZIF and 2nd SIF. Second narrow-band gain control loop for 2nd SIF via FM PLL.
8.7 Mono sound demodulator
8.7.1 Narrow-band FM PLL demodulation
Additional external input for either TV or radio intercarrier signal. FM carrier selection independent from VIF trap, because VIF trap uses reference via synthesizer. FM wide and ultra wide mode with adapted loop bandwidth and different selectable FM acquisition window widths to cope with FM overmodulation conditions.
8.7.2 AM sound demodulation
Passive AM sound detector. L and L-accent standard without SAW switching (done by sideband selection of SIF converter).
8.8 Audio amplifier
Different gain settings for FM sound to adapt to different FM deviation. Switchable de-emphasis for FM sound. Automatic mute function when FM PLL is unlocked. Forced mute function. Output amplifier for AM sound.
8.9 Synthesizer
In DIF mode, the synthesizer supports low and zero IF input frequencies for 34.5 MHz, 36 MHz, 44 MHz and 57 MHz center frequencies. In radio mode, the synthesizer supports 2nd sound intercarrier conversion. A large set of synthesizer frequencies in steps of 0.5 MHz enables flexible combination of filter and 2nd IF frequencies. Synthesizer loop internally adapted to divider ratio range for optimum phase noise requirement (loop bandwidth).
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
17 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Synthesizer reference either via 4 MHz crystal or via an external source. Individual pins for crystal and external reference allows optimum interface definition and supports use of custom reference frequency offset.
8.10 I2C-bus transceiver and slave address
Four different I2C-bus device addresses to enable application with multi-IC use. I2C-bus transceiver input ports can handle three different I2C-bus voltages. Read-out functions as TDA9887 plus additional read out of VIF AGC and TAGC status.
Table 4. Slave address detection Selectable address bit A3 MAD1 MAD2 MAD3 MAD4 0 0 1 1 A0 1 0 1 0 GND VP resistor to GND resistor to VP Pin ADRSEL
Slave address
9. I2C-bus control
Table 5. Name MAD1 MAD2 MAD3 MAD4
[1]
Slave addresses[1] Bit A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 0 0 1 1 A2 0 0 0 0 A1 1 1 1 1 A0 1 0 1 0 Value 43h 42h 4Bh 4Ah
Slave address
For MAD activation via pin ADRSEL: see Table 4.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
18 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
9.1 Read format
S
BYTE 1 A6 to A0 slave address R/W 1
A
BYTE 2 D7 to D0 data (R1)
A
BYTE 3 D7 to D0 data (R2)
NA
P
from master to slave
from slave to master
S = START condition A = acknowledge NA = not acknowledge P = STOP condition
001aad167
Fig 7. I2C-bus read format (slave transmits data) Table 6. 7 AFCWIN Table 7. Bit 7 R1 - data read register 1 bit allocation 6 reserved 5 CARRDET 4 AFC4 3 AFC3 2 AFC2 1 AFC1 0 PONR
R1 - data read register 1 bit description Symbol AFCWIN Description AFC window[1] 1 = VCO in 1.6 MHz AFC window[2] 1 = VCO in 0.8 MHz AFC window[3] 0 = VCO out of 1.6 MHz AFC window[2] 0 = VCO out of 0.8 MHz AFC window[3]
6 5
CARRDET
reserved FM carrier detection[4] 1 = detection (FM PLL is locked and level is less than 6 dB below gain controlled range of FM AGC) 0 = no detection
4 to 1 0
AFC[4:1] PONR
automatic frequency control; see Table 8 power-on reset 1 = after power-on reset or after supply breakdown 0 = after a successful reading of the status register
[1] [2] [3] [4]
If no IF input is applied, then bit AFCWIN can be logic 1 due to the fact that the VCO is forced to the AFC window border for fast lock-in behavior. All standards except M/N standard. M/N standard. Typical time constant of FM carrier detection is 50 ms. The minimal recommended wait time for read out is 80 ms.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
19 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Automatic frequency control bits[1] f[2] AFC3 R1[3] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 AFC2 R1[2] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 AFC1 R1[1] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 (fnom - 187.5 kHz) fnom - 162.5 kHz fnom - 137.5 kHz fnom - 112.5 kHz fnom - 87.5 kHz fnom - 62.5 kHz fnom - 37.5 kHz fnom - 12.5 kHz fnom + 12.5 kHz fnom + 37.5 kHz fnom + 62.5 kHz fnom + 87.5 kHz fnom + 112.5 kHz fnom + 137.5 kHz fnom + 162.5 kHz (fnom + 187.5 kHz)
Table 8. Bit AFC4 R1[4] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[1] [2]
fnom is the nominal frequency. In ATV mode f means vision intermediate frequency; in radio mode f means radio intermediate frequency.
Table 9. 7 reserved Table 10. Bit 7 6
R2 - data read register 2 bit allocation 6 TAGC 5 VAGC5 4 VAGC4 3 VAGC3 2 VAGC2 1 VAGC1 0 VAGC0
R2 - data read register 2 bit description Symbol TAGC Description reserved tuner AGC 1 = active 0 = inactive
5 to 0
VAGC[5:0]
AGC level detector; VIF AGC in ATV mode, SIF AGC in radio mode and DIF AGC in DTV mode; see Table 11
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
20 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
AGC bits (for corresponding AGC characteristic see Figure 12) VAGC4 R2[4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VAGC3 R2[3] 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VAGC2 R2[2] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VAGC1 R2[1] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VAGC0 R2[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Typical VAGC(VIF) (V) 0 (TOP)[1] -0.04 -0.08 -0.12 -0.16 -0.20 -0.24 -0.28 -0.32 -0.36 -0.40 -0.44 -0.48 -0.52 -0.56 -0.60 -0.64 -0.68 -0.72 -0.76 -0.80 -0.84 -0.88 -0.92 -0.96 -1.00 -1.04 -1.08 -1.12 -1.16 -1.20 -1.24 -1.28 -1.32 -1.36 -1.40 -1.44 -1.48 -1.52
(c) NXP B.V. 2008. All rights reserved.
Table 11. Bit VAGC5 R2[5] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
TDA9897_TDA9898_3
Product data sheet
Rev. 03 -- 11 January 2008
21 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
AGC bits (for corresponding AGC characteristic see Figure 12) ...continued VAGC4 R2[4] 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAGC3 R2[3] 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VAGC2 R2[2] 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VAGC1 R2[1] 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VAGC0 R2[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Typical VAGC(VIF) (V) -1.56 -1.60 -1.64 -1.68 -1.72 -1.76 -1.80 -1.84 -1.88 -1.92 -1.96 -2.00 -2.04 -2.08 -2.12 -2.16 -2.20 -2.24 -2.28 -2.32 -2.36 -2.40 -2.44 -2.48 -2.52
Table 11. Bit VAGC5 R2[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[1]
The reference of 0 (TOP) can be adjusted via TOPPOS[4:0] (register W10; see Table 49 and Table 47) or via potentiometer at pin TOP2.
9.2 Write format
S
BYTE 1 A6 to A0 slave address R/W 0
A
BYTE 2 A7 to A0 subaddress
A
BYTE 3 bits 7 to 0 data 1
A
BYTE n bits 7 to 0 data n
A
P
from master to slave
S = START condition A = acknowledge P = STOP condition
001aad166
from slave to master
Fig 8. I2C-bus write format (slave receives data)
TDA9897_TDA9898_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
22 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
9.2.1 Subaddress
Table 12. 7 A7 Table 13. Bit 7 to 4 3 to 0 Table 14. Bit A3 0 0 0 0 0 0 0 0 1 1 Table 15. W1[2] W2[3] W3[4] W4[5] W5[6] W6[7] W7[8] W8[9] W9[10] W10[11]
[1] [2] [3] [4] [5] [6] [7]
W0 - subaddress register bit allocation 6 A6 5 A5 4 A4 3 A3 2 A2 1 A1 0 A0
W0 - subaddress register bit description Symbol A[7:4] A[3:0] Description has to be set to logic 0 subaddress; see Table 14
Subaddress control bits Mode A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 subaddress for register W1 subaddress for register W2 subaddress for register W3 subaddress for register W4 subaddress for register W5 subaddress for register W6 subaddress for register W7 subaddress for register W8 subaddress for register W9 subaddress for register W10
I2C-bus write register overview[1] 6 STD1 STD4 AMUTE BP FSFREQ0 TAGC0 0 0 0 5 STD0 STD3 FMUTE MPP2S1 SFREQ5 AGC2 SIFLEVEL 0 TAGCTC XPOTPOS 4 TV2 STD2 FMWIDE0 MPP2S0 SFREQ4 AGC1 VIDLEVEL 0 TOPNEG4 TOPPOS4 3 TV1 SB DEEMT 0 SFREQ3 FMWIDE1 OPSTATE EASY3 TOPNEG3 TOPPOS3 2 DUAL PLL DEEM IFIN1 SFREQ2 TWOFLO PORT EASY2 TOPNEG2 TOPPOS2 1 FM GATE AGAIN1 IFIN0 SFREQ1 0 FILOUTBP EASY1 TOPNEG1 TOPPOS1 0 EXTFIL TRAP AGAIN0 VIFIN SFREQ0 DIRECT NYQOFF EASY0 TOPNEG0 TOPPOS0 RADIO MOD RESCAR VIFLEVEL FSFREQ1 TAGC1 0 0 0
Register 7
DAGCSLOPE TAGCIS
The register setting after power-on is not specified. See Table 17 for detailed description of W1. See Table 24 for detailed description of W2. See Table 28 for detailed description of W3. See Table 30 for detailed description of W4. See Table 34 for detailed description of W5. See Table 38 for detailed description of W6.
(c) NXP B.V. 2008. All rights reserved.
TDA9897_TDA9898_3
Product data sheet
Rev. 03 -- 11 January 2008
23 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
[8] [9]
See Table 41 for detailed description of W7. See Table 43 for detailed description of W8.
[10] See Table 46 for detailed description of W9. [11] See Table 49 for detailed description of W10.
9.2.2 Description of data bytes
Table 16. 7 RADIO Table 17. Bit 7 W1 - data write register bit allocation 6 STD1 5 STD0 4 TV2 3 TV1 2 DUAL 1 FM 0 EXTFIL
W1 - data write register bit description Symbol RADIO Description FM mode 1 = radio 0 = ATV/DTV
6 and 5 4 and 3
STD[1:0] TV[2:1]
2nd sound IF; see Table 18 and Table 19 TV mode 00 = DTV and ZIF 01 = DTV and LIF 10 = not defined 11 = ATV and QSS
2
DUAL
ATV and DTV dual mode for channel search; see Table 22 1 = dual (TV2 = 0) 0 = normal
1 and 0 Table 18. Bit RADIO W1[7] 0 0 0 0 0
[1]
FM and EXTFIL FM and output switching; see Table 21 Intercarrier sound BP and FM PLL frequency select for ATV, QSS mode[1] MOD W2[7] 1 1 1 1 0 STD1 W1[6] 0 0 1 1 1 STD0 W1[5] 0 1 0 1 1 FSFREQ1 FSFREQ0 TV1 W5[7] X X X X X W5[6] X X X X X W1[3] 1 1 1 1 1 4.5 5.5 6.0 6.5 off M/N standard B/G standard I standard D/K standard L/L-accent standard fFMPLL (MHz) Sound BP
For description of bit MOD refer to Table 24 and bits FSFREQ[1:0] are described in Table 34.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
24 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 19. Bit RADIO W1[7] 1 1 1 1 1
[1]
Intercarrier sound BP and FM PLL frequency select for radio, QSS mode[1] MOD W2[7] 1 1 1 1 0 STD1 W1[6] X X X X X STD0 W1[5] X X X X X FSFREQ1 FSFREQ0 TV1 W5[7] 0 0 1 1 X W5[6] 0 1 0 1 X W1[3] 0 0 0 0 0 4.5 5.5 6.0 6.5 10.7 M/N standard B/G standard I standard D/K standard RADIO fFMPLL (MHz) Sound BP
For description of bit MOD refer to Table 24 and bits FSFREQ[1:0] are described in Table 34.
Table 20. Bit BP W4[6] 0
[1]
Second sound IF selection for 10.7 MHz[1] fFMPLL (MHz) MOD W2[7] 0 RADIO W1[7] 1 10.7
For description of bit MOD refer to Table 24 and for BP refer to Table 30.
Table 21. MOD 1 1 1 1 0 0 0 0 FM 0 0 1 1 0 0 1 1
2nd intercarrier and sound input and output switching EXTFIL Mode 0 1 0 1 0 1 0 1 Input signal selection Signal at OUT1A and OUT1B (input switch) (output switch) internal BP via FM AGC internal BP internal BP external BP via FM AGC internal BP internal BP external BP Mono sound demodulation internal BP external BP external input external BP internal BP internal BP internal BP
W2[7] W1[1] W1[0]
FM sound internal FM sound EXTFILI FM sound EXTFMI FM sound EXTFILI AM sound not used AM sound AM sound AM sound EXTFILI
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
25 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
BYPASS
output switch OUT1A OUT1B
BAND-PASS
W7.1 = 0
W7.1 = 1
FM switch external filter output external filter input FM AGC amplifier FM PLL
3 dB
external FM input
EXTFILI EXTFILO EXTFMI
001aad351
Fig 9. Signal path for intercarrier (2nd SIF) processing Table 22. Bit TV2 W1[4] X 0 0 0 TV1 W1[3] X X 0 1 DIRECT DUAL W6[0] X 1 0 0 W1[2] 0 1 1 1 all normal mode functions (ATV OR DTV) analog CVBS at pin CVBS AND direct 1st DIF at pins OUT2A and OUT2B analog CVBS at pin CVBS AND digital zero IF I/Q at pins OUT1A, OUT1B and OUT2A, OUT2B analog CVBS at pin CVBS AND digital low IF at pins OUT1A and OUT1B Dual mode options Output mode
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
26 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
W2 - data write register bit allocation 6 STD4 5 STD3 4 STD2 3 SB 2 PLL 1 GATE 0 TRAP
Table 23. 7 MOD Table 24. Bit 7
W2 - data write register bit description Symbol MOD Description modulation 1 = negative; FM mono sound at ATV and dual mode 0 = positive; AM mono sound at ATV and dual mode
6 to 4 3
STD[4:2] SB
vision IF; see Table 25 sideband for sound IF and digital low IF 1 = upper 0 = lower
2 1
PLL GATE
operating modes; see Table 26 PLL gating 1 = on 0 = off
0
TRAP
sound trap 1 = on 0 = bypass
Table 25. Bit NYQOFF W7[0] X X X X X 0 1 X X X X X X X X X X
Vision IF fVIF (MHz) MOD W2[7] 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 STD4 W2[6] 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 STD3 W2[5] 0 0 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 STD2 W2[4] 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 38.0 38.375 38.875 39.875 32.25 32.625 33.9 33.125 33.625 38.0 38.375 38.875 39.875 45.75 58.75 46.25 59.25 low low low low high high high high low low low low low low low low TV1 = 1 (QSS) Sideband
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
27 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
VIF PLL gating and detector mode Gating and detector mode PLL W2[2] 0 1 0 1 0 % gating in positive modulation mode (W2[1] = 1) 36 % gating in positive modulation mode (W2[1] = 1) mode on; optimized for overmodulation in negative modulation mode; fPC = 0 kHz 187.5 kHz mode off; optimized for multipath in negative modulation mode; fPC = 0 kHz 187.5 kHz
Table 26. Bit MOD W2[7] 0 0 1 1
Table 27. 7 RESCAR Table 28. Bit 7
W3 - data write register bit allocation 6 AMUTE 5 FMUTE 4 FMWIDE0 3 DEEMT 2 DEEM 1 AGAIN1 0 AGAIN0
W3 - data write register bit description Symbol RESCAR Description video gain correction for residual carrier 1 = 20 % residual carrier 0 = 10 % residual carrier
6
AMUTE
auto mute 1 = on 0 = off
5
FMUTE
forced mute 1 = on 0 = off
4
FMWIDE0
FM window (W6[3] = 0) 1 = 475 kHz; normal FM phase detector steepness 0 = 237.5 kHz; high FM phase detector steepness
3
DEEMT
de-emphasis time 1 = 50 s 0 = 75 s
2
DEEM
de-emphasis 1 = on 0 = off
1 and 0
AGAIN[1:0]
audio gain 00 = 0 dB 01 = -6 dB 10 = -12 dB (only for FM mode) 11 = -18 dB (only for FM mode)
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
28 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
W4 - data write register bit allocation 6 BP 5 MPP2S1 4 MPP2S0 3 0 2 IFIN1 1 IFIN0 0 VIFIN
Table 29. 7 VIFLEVEL Table 30. Bit 7
W4 - data write register bit description Symbol VIFLEVEL Description control of internal VIF mixer input level (W1[4] = 1) and OUT1/OUT2 output level; see Table 31 1 = reduced 0 = normal
6
BP
SIF/DIF BP 1 = on (bit W6[0] = 0; see Table 38) 0 = bypass
5 and 4 3 2 and 1
MPP2S[1:0] IFIN[1:0]
AGC or AFC output; see Table 32 0 = fixed value DIF/SIF input 00 = IF1A/B input 01 = IF3A/B input 10 = not used 11 = IF2A/B input
0
VIFIN
VIF input 1 = IF1A/B input 0 = IF2A/B input
Table 31. Bit TV2 W1[4] 0 0 0 1 1 1 1
[1] [2]
List of output signals at OUT1 and OUT2 Output signal at TV1 W1[3] 0 1 X X X X X DIRECT W6[0] 0 0 1 X X X X FM W1[1] X X X 0 0 1 1 EXTFIL W1[0] X X X 0 1 0 1 zero IF I low IF off intercarrier[1] intercarrier[2] intercarrier[2] intercarrier[1] zero IF Q off direct IF off off off off OUT1A, OUT1B OUT2A, OUT2B
Intercarrier output level based on wide-band AGC of SIF amplifier. Intercarrier output level based on narrow-band AGC of FM amplifier.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
29 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Output mode at pin MPP2 for ATV; dual or radio mode Pin MPP2 output mode MPP2S1 W4[5] 0 0 1 1 1 MPP2S0 W4[4] 0 1 0 1 1 gain control voltage of FM PLL gain control voltage of SIF amplifier TAGC monitor voltage AFC current output, VIF PLL AFC current output, radio mode
Table 32. Bit RADIO W1[7] X X X 0 1 Table 33. 7
W5 - data write register bit allocation 6 5 SFREQ5 4 SFREQ4 3 SFREQ3 2 SFREQ2 1 SFREQ1 0 SFREQ0
FSFREQ1 FSFREQ0 Table 34. Bit 7 and 6
W5 - data write register bit description[1] Symbol FSFREQ[1:0] Description DTV filter or sound trap selection for video ATV; sound trap; TV2 = 1 00 = M/N standard (4.5 MHz) 01 = B/G standard (5.5 MHz) 10 = I standard (6.0 MHz) 11 = D/K and L/L-accent standard (6.5 MHz) DTV (zero IF); low-pass cut-off frequency; TV2 = 0 and TV1 = 0 00 = 3.0 MHz 01 = 3.5 MHz 10 = 4.0 MHz 11 = not used DTV (low IF); upper BP cut-off frequency; TV2 = 0 and TV1 = 1 00 = 7.0 MHz 01 = 8.0 MHz 10 = 9.0 MHz 11 = not used
5 to 0
[1]
SFREQ[5:0]
synthesizer frequencies; see Table 35 and Table 36
For bit description of TV1 and TV2 see Table 16 W1[3] and W1[4] and Table 17.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
30 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) fsynth (MHz) SFREQ4 W5[4] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SFREQ3 W5[3] 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 SFREQ2 W5[2] 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 SFREQ1 W5[1] 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SFREQ0 W5[0] 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 22.0 22.5 23.0 23.5 24.0 24.5 25.0 25.5 26.0 26.5 27.0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 37.5 38.0 38.5 39.0 39.5 40.0 40.5 41.0
(c) NXP B.V. 2008. All rights reserved.
Table 35. Bit SFREQ5 W5[5] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0
TDA9897_TDA9898_3
Product data sheet
Rev. 03 -- 11 January 2008
31 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
DIF/SIF synthesizer frequencies (using bit TWOFLO = 0) ...continued fsynth (MHz) SFREQ4 W5[4] 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SFREQ3 W5[3] 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SFREQ2 W5[2] 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SFREQ1 W5[1] 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SFREQ0 W5[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 41.5 42.0 42.5 43.0 43.5 44.0 44.5 45.0 45.5 46.0 46.5 47.0 47.5 48.0 48.5 49.0 49.5 50.0 50.5 51.0 51.5 52.0 52.5 53.0 53.5
Table 35. Bit SFREQ5 W5[5] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 36. Bit SFREQ5 W5[5] 1
DIF/SIF synthesizer frequency for zero IF Japan (using bit TWOFLO = 1) fsynth (MHz) SFREQ4 W5[4] 1 SFREQ3 W5[3] 0 SFREQ2 W5[2] 0 SFREQ1 W5[1] 1 SFREQ0 W5[0] 0 57
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
32 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
W6 - data write register bit allocation 6 TAGC0 5 AGC2 4 AGC1 3 FMWIDE1 2 TWOFLO 1 0 0 DIRECT
Table 37. 7 TAGC1 Table 38. Bit 7 and 6
W6 - data write register bit description Symbol TAGC[1:0] Description tuner AGC mode[1] 00 = TAGC integral loop mode; all currents off 01 = TAGC integral loop mode; source current off 10 = TAGC integral loop mode 11 = TAGC derived from IF AGC; recommended for positive modulated signals
5 and 4 3
AGC[2:1] FMWIDE1
AGC mode and behavior; see Table 39 FM window 1 = 1 MHz 0 = see Table 28 bit FMWIDE0
2
TWOFLO
synthesizer frequency selection 1 = zero IF Japan mode (57 MHz) 0 = synthesizer mode
1 0
DIRECT
0 = fixed value direct IF at DTV mode; TV2 = 0[2] 1 = direct IF output 0 = zero IF or low IF output
[1] [2]
In integral TAGC loop mode the pin TAGC provides sink and source currents for control. TakeOver Point (TOP) is set via register W9 TOPNEG[4:0]. For bit description refer to Table 16 and Table 17.
Table 39. Bit AGC2 W6[5] 0 0 1 1
[1]
AGC mode and behavior VIF AGC; MOD = 1[1] AGC1 W6[4] 0 1 0 1 normal off (minimum gain) fast 2nd fast normal off (minimum gain) normal fast SIF AGC
For bit description of MOD refer to Table 23 W2[7] and Table 24.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
33 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
W7 - data write register bit allocation 6 0 5 4 3 2 PORT 1 0 SIFLEVEL VIDLEVEL OPSTATE FILOUTBP NYQOFF
Table 40. 7 0 Table 41. Bit 7 and 6 5
W7 - data write register bit description Symbol Description 0 = fixed value 1 = internal SIF level is reduced by 6 dB (only for AM sound) 0 = internal SIF level is normal
SIFLEVEL SIF level reduction
4
VIDLEVEL video level reduction 1 = internal video level is reduced by 6 dB 0 = internal video level is normal
3
OPSTATE
output state; PORT = 1 1 = output port is HIGH (external pull-up resistor needed) 0 = output port is LOW
2
PORT
port or VIF AGC monitor 1 = pin MPP1 is logic output port; level depends on OPSTATE 0 = pin MPP1 is VIF AGC monitor output; independent on OPSTATE
1
FILOUTBP external filter output signal source; see Figure 9 1 = signal for external filter is obtained behind internal BP filter 0 = signal for external filter is obtained behind SIF mixer
0
NYQOFF
internal Nyquist processing 1 = internal Nyquist processing off[1] 0 = internal Nyquist processing on
[1]
At internal Nyquist processing off (W7[0] = 1) it is mandatory to set the internal video level bit VIDLEVEL to normal (W7[4] = 0).
Table 42. 7 0 Table 43. Bit 7 to 4 3 to 0
W8 - data write register bit allocation 6 0 5 0 4 0 3 EASY3 2 EASY2 1 EASY1 0 EASY0
W8 - data write register bit description Symbol EASY[3:0] Description 0 = fixed value easy setting; see Table 44
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
34 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 44. Bit EASY3 W8[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
[1]
Easy setting (to be used for fixed bit set-up only)[1] EASY2 W8[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 EASY1 W8[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 EASY0 W8[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 off I 6.0 B/G 5.5 direct IF M Japan 4.5 LIF 6/36 D/K 6.5 radio 5.5 L 6.5 ES2 ES3 ES4 ES5 ES6 ES8 ES9 ES11 58 38 08 18 28 78 BB 79 B1 B1 E1 F1 88 B1 B8 33 CC 4C 64 44 60 4C 40 00 60 60 62 73 61 70 26 60 80 40 00 00 AD C0 6B C0 80 80 81 80 00 80 00 C0 0C 0C 08 08 0C 0C 04 0C Mode or standard Name Bit definition (hexadecimal) W1 W2 W3 W4 W5 W6 W7
Access to register W1 to W6 after selection of an easy setting mode would require a transfer of all W1 to W6 register data.
Table 45. 7
W9 - data write register bit allocation 6 TAGCIS 5 TAGCTC 4 TOPNEG4 3 TOPNEG3 2 TOPNEG2 1 TOPNEG1 0 TOPNEG0
DAGCSLOPE Table 46. Bit 7
W9 - data write register bit description Symbol DAGCSLOPE Description AGCDIN input characteristic; see Figure 45 1 = high voltage for high gain 0 = low voltage for high gain
6
TAGCIS
tuner AGC IF input 1 = inverse to VIF input 0 = aligned to VIF input
5
TAGCTC
tuner AGC time constant 1 = 2nd mode 0 = normal
4 to 0
TOPNEG[4:0]
TOP adjustment for integral loop mode; see Table 47
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
35 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Tuner takeover point adjustment bits W9[4:0] TOP adjustment (dBV) TOPNEG3 W9[3] 1 : 0 : 0 TOPNEG2 W9[2] 1 : 0 : 0 TOPNEG1 W9[1] 1 : 0 : 0 TOPNEG0 W9[0] 1 : 0 : 0 98.2 typical see Figure 13 78.7[1] see Figure 13 57.9 typical
Table 47. Bit TOPNEG4 W9[4] 1 : 1 : 0
[1]
See Table 53 for parameter tuner takeover point accuracy (acc(set)TOP).
Table 48. 7 0 Table 49. Bit 7 and 6 5
W10 - data write register bit allocation 6 0 5 4 3 2 1 0 XPOTPOS TOPPOS4 TOPPOS3 TOPPOS2 TOPPOS1 TOPPOS0
W10 - data write register bit description Symbol XPOTPOS Description 0 = fixed value TOP derived from IF AGC via I2C-bus or potentiometer 1 = TOP adjustment by external potentiometer at pin TOP2 0 = see Table 50
4 to 0 Table 50. Bit TOPPOS4 W10[4] 1 : 1 : 0
[1]
TOPPOS[4:0] TOP adjustment for TAGC derived from IF AGC; see Table 50 Tuner takeover point adjustment bits W10[4:0] TOP adjustment (dBV) TOPPOS3 W10[3] 1 : 0 : 0 TOPPOS2 W10[2] 1 : 0 : 0 TOPPOS1 W10[1] 1 : 0 : 0 TOPPOS0 W10[0] 1 : 0 : 0 99 typical see Figure 13 81[1] see Figure 13 61 typical
See Table 53 for parameter tuner takeover point accuracy (acc(set)TOP2).
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
36 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
10. Limiting values
Table 51. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VP Vn tsc Tstg Tamb Tcase Parameter supply voltage voltage on any other pin short-circuit time storage temperature ambient temperature case temperature TDA9898HL (LQFP48) TDA9898HN (HVQFN48) TDA9897HL (LQFP48) TDA9897HN (HVQFN48) Vesd electrostatic discharge voltage human body model machine model
[1] [2] Class 2 according to JESD22-A114. Class B according to EIA/JESD22-A115.
[1] [2]
Conditions all pins except ground to ground or VP
Min Max 0 5.5 VP 10
Unit V V s C C C C C C V
-40 +150 -20 +70 105 115 105 115 300
3000 V
11. Thermal characteristics
Table 52. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient TDA9898HL (LQFP48) TDA9898HN (HVQFN48) TDA9897HL (LQFP48) TDA9897HN (HVQFN48) Rth(j-c) thermal resistance from junction to case TDA9898HL (LQFP48) TDA9898HN (HVQFN48) TDA9897HL (LQFP48) TDA9897HN (HVQFN48) 19 10 19 10 K/W K/W K/W K/W Conditions in free air; 2 layer board 67 48 67 48 K/W K/W K/W K/W Typ Unit
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
37 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
12. Characteristics
12.1 Analog TV signal processing
Table 53. Characteristics VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Supply; pin VP VP IP Power-on reset VP(POR) power-on reset supply voltage for start of reset at decreasing supply voltage for end of reset at increasing supply voltage; I2C-bus transmission enable VIF amplifier; pins IF1A, IF1B, IF2A and IF2B VI Ri(dif) Ci(dif) Vi(IF)(RMS) input voltage differential input resistance differential input capacitance RMS IF input voltage lower limit at -1 dB video output signal upper limit at +1 dB video output signal permissible overload GIF IF gain variation difference between picture and sound carrier; within AGC range; f = 5.5 MHz
[4] [3] [3] [2]
Parameter supply voltage supply current
Conditions
[1]
Min 4.5 2.5 -
Typ 5.0 3.0 3.3
Max 5.5 190 3.5 4.4
Unit V mA V V
[2]
150 -
1.95 2 3 60 190 0.7
100 320 -
V k pF V mV mV dB
GVIF(cr) f-3dB(VIF)l f-3dB(VIF)u VLFVIF fVCO(max) fVIF fVIF(dah)
control range VIF gain lower VIF cut-off frequency upper VIF cut-off frequency demodulator[5] voltage on pin LFVIF (DC) maximum VCO frequency VIF frequency digital acquisition help VIF frequency window fVCO = 2fPC see Table 25 related to fVIF all standards except M/N M/N standard BLF(-3dB) = 70 kHz
[6]
60 0.9 120 -
66 15 80 140 2.3 1.8 -
3.6 30
dB MHz MHz V MHz MHz MHz MHz ms
FPLL and true synchronous video
tacq
TDA9897_TDA9898_3
acquisition time
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
38 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Vlock(min)(RMS) Parameter RMS minimum lock-in voltage Conditions measured on pins IF1A and IF1B or IF2A and IF2B; maximum IF gain; negative modulation mode W2[7] = 1 and PLL set to overmodulation mode W2[2] = 0 and W2[1] = 0 Min Typ 30 Max 70 Unit V
Tcy(dah) tw(dah) Ipul(acq)VIF KO(VIF) KD(VIF) Ioffset(VIF)
digital acquisition help cycle time digital acquisition help pulse width VIF acquisition pulse current VIF VCO steepness VIF phase detector steepness VIF offset current CVBS[7] positive or negative modulation; see Figure 10 W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 W4[7] = 1; W7[4] = 1 sink or source fVIF / VLFVIF IVPLL / VCO(VIF)
64 21 -1
64 26 23 0
33 +1
s s A MHz/V A/rad A
Video output 2 V; pin Vo(video)(p-p)
Normal mode (sound carrier trap active) and sound carrier on peak-to-peak video output voltage
1.7 1.7 1.7 -
2.0 2.0 2.0 2.0
2.3 2.3 2.3 -
V V V V
Vo(CVBS)
CVBS output voltage difference
difference between L and B/G standard W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 -240 -240 -240 2.0 W4[7] = 0; W7[4] = 0 W4[7] = 1; W7[4] = 0 W4[7] = 0; W7[4] = 1 1.0 0.9 0.9 [3]
2.33 1.2 1.2 1.2 0.4 2.0 -
+240 +240 +240 2.75 1.4 1.5 1.5 0.9 30 -
mV mV mV
Vvideo/Vsync Vsyncl
video voltage to sync voltage ratio sync level voltage
V V V V V mA mA
Vclip(video)u Vclip(video)l RO Ibias(int) Isink(o)(max)
TDA9897_TDA9898_3
upper video clipping voltage lower video clipping voltage output resistance internal bias current (DC) for emitter-follower maximum output sink current AC and DC
VP - 1.2 VP - 1 1.5 1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
39 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Isource(o)(max) Vo(CVBS) Vblt/VCVBS Vblt(v)/VCVBS Parameter maximum output source current CVBS output voltage difference black level tilt to CVBS voltage ratio vertical black level tilt to CVBS voltage ratio Conditions AC and DC 50 dB gain control 30 dB gain control negative modulation worst case in L standard; vision carrier modulated by test line [Vertical Interval Test Signal (VITS)] only Min 3.9 Typ Max 0.5 0.1 1 3 Unit mA dB dB % %
Gdif
differential gain
"ITU-T J.63 line 330"
B/G standard L standard
[8]
[8]
2 2 57
5 7 4 4 -
% % deg deg dB
dif
differential phase
"ITU-T J.63 line 330"
B/G standard L standard
[9]
(S/N)w
weighted signal-to-noise ratio B/G standard; 50 % grey video signal; unified weighting filter ("ITU-T J.61"); see Figure 20 unweighted signal-to-noise ratio RMS residual picture carrier voltage peak-to-peak picture carrier frequency variation phase difference M/N standard; 50 IRE grey video signal; see Figure 20 fundamental wave and harmonics 3 % residual carrier; 50 % serration pulses; L standard 0 % residual carrier; 50 % serration pulses; L standard; L-gating = 0 %
53
(S/N)unw
47
51
-
dB
VPC(rsd)(RMS) fPC(p-p)
[3]
2 -
5 12
mV kHz
-
[3]
-
-
3
%
H(video) sp PSRRCVBS
video harmonics suppression AC load: CL < 20 pF, RL > 1 k spurious suppression power supply ripple rejection on pin CVBS fripple = 70 Hz; video signal; grey level; positive and negative modulation; see Figure 11
[10]
35 40 14
40 20
-
dB dB dB
[11]
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
40 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol ripple(resp)f Parameter 21[12] 0.5 MHz to 2.5 MHz 2.5 MHz to 3.6 MHz 3.6 MHz to 3.8 MHz 3.8 MHz to 4.2 MHz SC1 SC2 td(grp)CC first sound carrier attenuation f = fSC1 = 4.5 MHz f = fSC1 60 kHz second sound carrier attenuation f = fSC2 = 4.724 MHz f = fSC2 60 kHz
[13]
Conditions
Min -1 -2 -3 -16 38 29 25 16 -75
Typ -50
Max +1 +2 +2 +2 +75
Unit dB dB dB dB dB dB dB dB ns
M/N standard inclusive Korea; see Figure
frequency response ripple
color carrier group delay time f = 3.58 MHz; including transmitter pre-correction; see Figure 22 frequency response ripple 0.5 MHz to 3.2 MHz 3.2 MHz to 4.5 MHz 4.5 MHz to 4.8 MHz 4.8 MHz to 5 MHz
B/G standard; see Figure 23[12] ripple(resp)f -1 -2 -4 -12 35 26 25 16 12 21 5
[13]
-10
+1 +2 +2 +2 +75
dB dB dB dB dB dB dB dB dB dB dB ns
SC1 SC2 SC(NICAM) td(grp)CC
first sound carrier attenuation f = fSC1 = 5.5 MHz f = fSC1 60 kHz second sound carrier attenuation NICAM sound carrier attenuation attenuation f = fSC2 = 5.742 MHz f = fSC2 60 kHz fcar(NICAM) = 5.85 MHz; f = fcar(NICAM) 250 kHz f = f(N+1)ch = 7 MHz f = f(N+1)ch 750 kHz color carrier group delay time f = 4.43 MHz; including transmitter pre-correction; see Figure 24 frequency response ripple 0.5 MHz to 3.2 MHz 3.2 MHz to 4.5 MHz 4.5 MHz to 5 MHz 5 MHz to 5.5 MHz
-75
I standard; see Figure 25[12] ripple(resp)f -1 -2 -4 -12 35 26 12 +1 +2 +2 +2 dB dB dB dB dB dB dB
SC1 SC(NICAM)
first sound carrier attenuation f = fSC1 = 6.0 MHz f = fSC1 60 kHz NICAM sound carrier attenuation fcar(NICAM) = 6.55 MHz; f = fcar(NICAM) 250 kHz
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
41 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol td(grp)CC Parameter Conditions
[13]
Min -75
Typ -15
Max +75
Unit ns
color carrier group delay time f = 4.43 MHz; see Figure 26 frequency response ripple 0.5 MHz to 3.1 MHz 3.1 MHz to 4.5 MHz 4.5 MHz to 4.8 MHz 4.8 MHz to 5.1 MHz
D/K standard; see Figure 27[12] ripple(resp)f -1 -2 -4 -6 35 26 25 16 25 16 6
[13]
0
+1 +2 +2 +2 +100
dB dB dB dB dB dB dB dB dB dB dB ns
SC1 SC2(us) SC2(ls) SC(NICAM) td(grp)CC
first sound carrier attenuation f = fSC1 = 6.5 MHz f = fSC1 60 kHz second sound carrier attenuation (upper side) second sound carrier attenuation (lower side) NICAM sound carrier attenuation f = fSC2 = 6.742 MHz f = fSC2 60 kHz f = fSC2 = 6.258 MHz f = fSC2 60 kHz fcar(NICAM) = 5.85 MHz; f = fcar(NICAM) 250 kHz
color carrier group delay time f = 4.28 MHz; including transmitter pre-correction; see Figure 28 frequency response ripple 0.5 MHz to 3.2 MHz 3.2 MHz to 4.5 MHz 4.5 MHz to 4.8 MHz 4.8 MHz to 5.3 MHz
-50
L standard; see Figure 29[12] ripple(resp)f -1 -2 -4 -12 5 38 29 -75 -5 +1 +2 +2 +2 +75 dB dB dB dB dB dB dB ns
SC(NICAM) SC(AM) td(grp)CC
NICAM sound carrier attenuation
fcar(NICAM) = 5.85 MHz; f = fcar(NICAM) 250 kHz f = fSC(AM) 30 kHz
AM sound carrier attenuation f = fSC(AM) = 6.5 MHz color carrier group delay time f = 4.28 MHz; including transmitter pre-correction; see Figure 30
Video output 1.1 V; pin CVBS Trap bypass mode and sound carrier off[12] Vo(video)(p-p) Vsyncl Vclip(video)u Vclip(video)l Bvideo(-3dB) peak-to-peak video output voltage sync level voltage upper video clipping voltage lower video clipping voltage -3 dB video bandwidth AC load: CL < 20 pF, RL > 1 k see Figure 10 6 1.1 1.5 0.4 8 0.9 V V V V MHz
VP - 1.1 VP - 1
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
42 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol (S/N)w Parameter Conditions
[9]
Min 54
Typ -
Max -
Unit dB
weighted signal-to-noise ratio B/G standard; 50 % grey video signal; unified weighting filter ("ITU-T J.61"); see Figure 20 unweighted signal-to-noise ratio M/N standard; 50 IRE grey video signal; see Figure 20
(S/N)unw
[9]
47
51
-
dB
Loop filter synthesizer; pin LFSYN1 VLFSYN1 Isource(o)PD(max) Isink(o)PD(max) KO KD Vmonitor(VIFAGC) VAGC voltage on pin LFSYN1 maximum phase detector output source current maximum phase detector output sink current VCO steepness phase detector steepness VIF AGC monitor voltage AGC voltage see Figure 12; Vi(IF) set to 1 mV (60 dBV) 10 mV (80 dBV) 200 mV (106 dBV) Io(max) maximum output current sink or source 2.2 2.5 3 10 2.6 3.1 4 V V V A
[3]
1.0 0.5
3.75 9 -
3.5 65 65 4.5
V A A MHz/V A/rad V
Pin MPP1 operating as VIF AGC voltage monitor
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
43 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol tresp Parameter response time Conditions increasing VIF step; negative modulation normal mode fast mode increasing VIF step; positive modulation; normal mode decreasing VIF step; negative modulation normal mode fast normal mode 2nd mode fast 2nd mode decreasing VIF step; positive modulation 20 dB fast mode normal mode th(fast)VIF VVAGC(step) VIF fast mode threshold VIF AGC voltage difference (step) LOW-level output voltage output sink current HIGH-level output voltage maximum charge current additional charge current L standard L standard: in the event of missing VITS pulses and no white video content L standard; normal mode L standard; fast mode L standard see Table 11
[14] [14] [14]
Min
Typ
Max
Unit
-
4.3 1.5 130
-
s/dB s/dB s/dB
[14]
-
1.9 0.08 0.25 0.01
-
ms/dB ms/dB ms/dB ms/dB
-10 -
890 2.6 143 -6 40
-2 -
ms ms/dB ms/dB dB mV/bit
Pin MPP1 operating as open-collector output port VOL Isink(o) VOH Ich(max) Ich(add) I = 2 mA (sink) W7[3] = 0 W7[3] = 1 VIF AGC; pin CIFAGC 75 100 100 125 A nA 0.4 3 10 V mA A
VP + 0.5 V
Idch
discharge current
-
35 1.8
-
nA A
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
44 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tuner AGC; pin TAGC Integral TAGC loop mode (W6[7:6] = 10); TAGC is current output; applicable for negative modulation only; unmodulated VIF; see Table 46 and Figure 13 Vi(IF)(RMS) RMS IF input voltage at starting point of tuner AGC takeover; Isink(TAGC) = 100 A W9[4:0] = 0 0000 W9[4:0] = 1 0000 W9[4:0] = 1 1111 acc(set)TOP Isource TOP setting accuracy source current TAGC charge current normal mode; W9[5] = 0 2nd normal mode; W9[5] = 1 fast mode activated by internal level detector; W9[5] = 0 2nd fast mode activated by internal level detector; W9[5] = 1 Isink acc(set)TOP/T RL Vsat(u) Vsat(l) th(fast)AGC sink current TOP setting accuracy variation with temperature load resistance upper saturation voltage lower saturation voltage AGC fast mode threshold pin operating as current output pin operating as current output activated by internal fast AGC detector; I2C-bus setting corresponds to W9[4:0] = 1 0000 before activating; Vi(IF) below th(fast)AGC
[3]
-2 0.2 1.9 7
57.9 78.7 98.2 0.3 2.3 11
+2 0.4 2.7 15
dBV dBV dBV dB A A A
60
90
120
A
TAGC discharge current; VTAGC = 1 V W9[4:0] = 1 0000
[3]
400 50
500 -
600 0.02 0.3 10
A dB/K M V V dB
VP - 0.3 6 8
td
delay time
40
60
80
ms
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
45 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit TAGC loop based on VIF AGC (W6[7:6] = 11); TAGC is voltage output; applicable for TV mode: positive modulation and optional for negative modulation); see Table 49; Figure 13 and Figure 14 Vi(IF)(RMS) RMS IF input voltage at starting point of tuner AGC takeover; VTAGC = 3.5 V RTOP2 = 22 k or W10[5:0] = 00 0000 RTOP2 = 10 k or W10[5:0] = 01 0000 RTOP2 = 0 k W10[5:0] = 01 1111 acc(set)TOP2 TOP2 setting accuracy VTAGC = 3.5 V no tuner gain reduction maximum tuner gain reduction Gslip(TAGC) TAGC slip gain offset tuner gain voltage from 0.6 V to 3.5 V pin open-circuit adjustment of VIF AGC based TAGC loop W10[5] = 1; external resistor operation W10[5] = 0; forced I2C-bus operation Pin CTAGC VCTAGC IL voltage on pin CTAGC leakage current sink source Control current or voltage monitor output; pin MPP2 General Vsat(u) Vsat(l) upper saturation voltage lower saturation voltage VP - 0.8 VP - 0.5 0.5 0.8 V V
[3] [3] [3]
-6 4.5 0.2 3
61 81 96 99 0.03 5
+6 0.07 VP 0.6 8
dBV dBV dBV dBV dB dB/K V V dB
acc(set)TOP2/T TOP2 setting accuracy variation with temperature VO output voltage
TOP adjust 2; pin TOP2; IF based TAGC loop mode; see Figure 14 VTOP2 RI RTOP2 voltage on pin TOP2 (DC) input resistance resistance on pin TOP2 3.5 27 V k
0 100
-
22 -
k k
0.2 -
-
0.55VP 10 10
V nA nA
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
46 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Io Parameter output current Conditions sink or source; see Figure 17 and Figure 18 100 kHz VIF deviation 200 kHz VIF deviation 1.5 MHz VIF deviation AFC TV mode IAFC/fVIF fVIFacc(dig) fVIFacc(a) AFC radio mode IAFC/fRIF fRIFacc(dig) fRIFacc(a) change of AFC current with RIF frequency digital accuracy of RIF frequency analog accuracy of RIF frequency voltage gain read-out via I2C-bus; R1[4:1] = f0; fref = 4 MHz IAFC = 0 A; fref = 4 MHz
[16] [15][16]
Min
Typ
Max
Unit
AFC (current output)
80 160 160
[16]
200 1.05 -
160 240 240 1.25 +20 +20
A A A A/kHz kHz kHz
change of AFC current with VIF frequency digital accuracy of VIF frequency analog accuracy of VIF frequency read-out via I2C-bus; R1[4:1] = f0; fref = 4 MHz IAFC = 0 A; fref = 4 MHz
0.85 -20 -20
[17]
[17]
0.85 -10 -10
1.05 -
1.25 +10 +10
A/kHz kHz kHz
[17]
[17]
AGC monitor (voltage output) Gv voltage on pin MPP2 to internal control voltage; see Table 32 SIF AGC FM AGC TAGC Io(max) VI Ri(dif) Ci(dif) maximum output current input voltage differential input resistance differential input capacitance sink or source SIF amplifier; pins IF3A and IF3B or pins IF1A and IF1B or pins IF2A and IF2B 1.95 2 3 V k pF 0 dB
350
6 6 0 -
-
dB dB dB A
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
47 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Vi(SIF)(RMS) Parameter RMS SIF input voltage Conditions FM mode; -3 dB at intercarrier output pins OUT1A and OUT1B; without FM AGC; see Table 21 AM mode; -3 dB at AF output pin AUD FM mode; +1 dB at intercarrier output pins OUT1A and OUT1B; without FM AGC; see Table 21 AM mode; +1 dB at AF output pin AUD permissible overload GSIF(cr) f-3dB(SIF)l f-3dB(SIF)u tresp control range SIF gain lower SIF cut-off frequency upper SIF cut-off frequency response time increasing or decreasing SIF step of 20 dB; AM mode; fast AGC increasing decreasing increasing or decreasing SIF step of 20 dB; AM mode; slow AGC increasing decreasing increasing or decreasing SIF step of 20 dB; FM mode; normal AGC increasing decreasing increasing or decreasing SIF step of 20 dB; FM mode; fast AGC increasing decreasing 0.1 4 ms ms 0.3 20 ms ms 80 250 ms ms 8 25 ms ms FM and AM mode Min Typ 60 Max 100 Unit V
150
40 190
70 -
V mV
70 60 -
140 66 7 80
320 -
mV mV dB MHz MHz
SIF AGC detector; pin MPP2; see Figure 16
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
48 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol VAGC(SIF) Parameter SIF AGC voltage Conditions FM mode VSIF = 100 V VSIF = 10 mV VSIF = 140 mV AM mode VSIF = 100 V VSIF = 10 mV VSIF = 140 mV Conversion synthesizer PLL; pin LFSYN2 (radio mode) VLFSYN2 KO KD voltage on pin LFSYN2 VCO steepness phase detector steepness fVCO / VLFSYN2 ILFSYN2 / VCO; see Table 57; fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz Io(PD) phase detector output current sink or source; fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz n(synth) synthesizer phase noise with 4 MHz crystal oscillator reference at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz sp IL spurious suppression leakage current multiple of f = 500 kHz synthesizer spurious performance > 50 dBc
[3] [3] [3] [3] [3] [3]
Min 1.5 2.6 3.3 1.5 2.9 3.3 1 -
Typ 31
Max 2.4 3.4 VP 2.4 3.9 VP 3 -
Unit V V V V V V V MHz/V
-
32 38 47 61 61
-
A/rad A/rad A/rad A/rad A/rad
-
200 238 294 384 384
-
A A A A A
89 89 98 115 50 -
99 99 102 119 -
10
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc nA
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
49 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol PSRR Parameter power supply ripple rejection Conditions residual spurious at nominal differential output voltage dependent on power supply ripple at 70 Hz; see Figure 11 Min Typ 50 Max Unit dB
Single reference QSS intercarrier mixer; pins OUT1A and OUT1B VOUT1A VOUT1B Ibias(int) Isink(o)(max) Isource(o)(max) RO voltage on pin OUT1A (DC) voltage on pin OUT1B (DC) internal bias current (DC) maximum output source current output resistance for emitter-follower DC and AC; with external resistor to GND output active; single-ended to GND output inactive; internal resistance to GND Vo(RMS) RMS output voltage IF intercarrier single-ended to GND; SC1 on; SC2 off IF intercarrier single-ended to GND; L standard; without modulation; BP on W7[5] = 0 W7[5] = 1 f-3dB(ic)u image Vinterf(RMS) upper intercarrier cut-off frequency image rejection RMS interference voltage internal sound band-pass off band-pass off; -8 MHz to 0 MHz fundamental wave and harmonics IF intercarrier; L standard; without modulation 45 20 11 24 70 35 15 28 2 90 45 5 mV mV MHz dB mV maximum output sink current DC and AC 1.8 1.8 2.0 1.4 3.0 90 2.0 2.0 2.5 1.7 800 140 2.2 2.2 25 180 V V mA mA mA mV
AM intercarrier from pin EXTFILI to pins OUT1A and OUT1B G gain 5 dB
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
50 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Band-pass mode fc center frequency QSS mode; BP selection for standard M/N B/G I D/K L/L-accent radio mode; BP selection for standard M/N B/G I D/K RADIO f-3dB(BP)u upper BP cut-off frequency M/N, B/G, I, D/K or L/L-accent standard RADIO 10.7 f-3dB(BP)l lower BP cut-off frequency M/N, B/G, I, D/K or L/L-accent standard RADIO 10.7 stpb stop-band attenuation at fc 1.5 MHz M/N, B/G, I, D/K or L/L-accent standard RADIO 10.7 CC color carrier attenuation QSS mode; BP selection for standard M/N; fCC = 3.58 MHz B/G; fCC = 4.43 MHz I; fCC = 4.43 MHz D/K; fCC = 4.28 MHz L/L-accent; fCC = 4.28 MHz External filter output; pin EXTFILO VEXTFILO voltage on pin EXTFILO (DC) 1.8 2.0 2.2 V 15 22 20 20 20 23 30 28 28 28 dB dB dB dB dB 20 15 30 25 dB dB fc + 0.5 4.7 5.75 6.25 6.78 10.7 MHz MHz MHz MHz MHz MHz 4.7 5.75 6.25 6.25 6.05 MHz MHz MHz MHz MHz Parameter Conditions Min Typ Max Unit
fc + 0.65 fc + 0.8
fc + 0.25 fc + 0.4 fc - 0.5
fc + 0.55 MHz MHz
fc - 0.65 fc - 0.8
fc - 0.25 fc - 0.4
fc - 0.55 MHz
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
51 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol VEXTFILO(p-p) Parameter peak-to-peak voltage on pin EXTFILO Conditions IF intercarrier; SC1 on; SC2 off IF intercarrier; L standard; without modulation W7[5] = 0 W7[5] = 1 Io(max) fFMPLL maximum output current FM PLL frequency AC and DC see Table 18 and Table 20 FM PLL demodulator FM PLL filter; pin LFFM VLFFM voltage on pin LFFM fFMPLL = 4.5 MHz fFMPLL = 5.5 MHz fFMPLL = 6.0 MHz fFMPLL = 6.5 MHz fFMPLL = 10.7 MHz Tcy(dah) tw(dah) Io(dah) digital acquisition help cycle time digital acquisition help pulse width digital acquisition help output sink or source current W3[4] = 0; W6[3] = 0; FM window width = 237.5 kHz W3[4] = 1; W6[3] = 0; FM window width = 475 kHz W3[4] = 0; W6[3] = 1; FM window width = 1 MHz W3[4] = 1; W6[3] = 1; FM window width = 1 MHz 1.5 1.5 1.5 1.5 1.5 1.9 2.2 2.35 2.5 2.4 64 16 3.3 3.3 3.3 3.3 3.3 V V V V V s s 4.5 5.5 6.0 6.5 10.7 MHz MHz MHz MHz MHz 210 105 1 310 155 410 205 mV mV mA Min 420 Typ 620 Max 820 Unit mV
14
18
22
A
28
36
44
A
14
18
22
A
28
36
44
A
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
52 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol KD(FM) Parameter FM phase detector steepness Conditions IFMPLL / VCO(FM) W3[4] = 0; W6[3] = 0; FM window width = 237.5 kHz W3[4] = 1; W6[3] = 0; FM window width = 475 kHz W3[4] = 0; W6[3] = 1; FM window width = 1 MHz W3[4] = 1; W6[3] = 1; FM window width = 1 MHz KO(FM) FM VCO steepness fFMPLL / VLFFM f < 10 MHz f = 10.7 MHz Ioffset(FM) FM offset current W6[3] = 0; W3[4] = 0 W6[3] = 0; W3[4] = 1 FM intercarrier input; pins EXTFMI and EXTFILI; see Figure 15 |Zi| Vi(FM)(RMS) input impedance RMS FM input voltage AC-coupled via 4 pF gain controlled operation; W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01 W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01 W1[1:0] = 10 or W1[1:0] = 11 or W1[1:0] = 01 QSS mode; 25 kHz FM deviation; 75 s de-emphasis QSS mode; 27 kHz FM deviation; 50 s de-emphasis QSS mode; 55 kHz FM deviation; 50 s de-emphasis radio mode; 22.5 kHz FM deviation; 75 s de-emphasis
TDA9897_TDA9898_3
Min -
Typ 4
Max -
Unit A/rad
-
10
-
A/rad
-
4
-
A/rad
-
10
-
A/rad
-1.5 -2.5 2
3.3 5.9 0 0 20 -
+1.5 +2.5 300
MHz/V MHz/V A A k mV
Vlock(min)(RMS)
RMS minimum lock-in voltage RMS minimum FM carrier detection voltage
-
-
1.5
mV
Vdet(FM)min(RMS)
-
-
1.8
mV
FM demodulator part; audio output; pin AUD Vo(AF)(RMS) RMS AF output voltage 400 500 600 mV
430
540
650
mV
900
-
1300
mV
360
450
540
mV
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
53 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol Vo(AF)/T THD Parameter AF output voltage variation with temperature total harmonic distortion 50 s de-emphasis; FM deviation: for TV mode 27 kHz and for radio mode 22.5 kHz THD < 2 %; pre-emphasis off; fAF = 400 Hz W3[1:0] = 00 (audio gain = 0 dB) W3[1:0] = 01 (audio gain = -6 dB) W3[1:0] = 10 (audio gain = -12 dB) W3[1:0] = 11 (audio gain = -18 dB) and W3[4] = 1 (FM window width = 475 kHz) fAF(max) maximum AF frequency THD < 2 %; pre-emphasis off FM window width = 237.5 kHz; -6 dB audio gain; FM deviation 100 kHz FM window width = 475 kHz; -18 dB audio gain; FM deviation 300 kHz f-3dB(AF) AF cut-off frequency W3[2] = 0; W3[4] = 0; without de-emphasis; FM window width = 237.5 kHz 27 kHz FM deviation; 50 s de-emphasis; vision carrier unmodulated; FM PLL only; "ITU-R BS.468-4" radio mode (10.7 MHz); 22.5 kHz FM deviation; 75 s de-emphasis fundamental wave and harmonics; without de-emphasis
[3] [18]
Conditions
Min -
Typ 3x 10-3
Max 7x 10-3
Unit dB/K %
0.15
0.50
fAF(max)
maximum AF frequency deviation
55 110 170 380
-
-
kHz kHz kHz kHz
15
-
-
kHz
15
-
-
kHz
80
100
-
kHz
(S/N)w(AF)
AF weighted signal-to-noise ratio
48
56
-
dB
(S/N)unw(AF)
AF unweighted signal-to-noise ratio RMS residual sound carrier voltage
-
58
-
dB
VSC(rsd)(RMS)
-
-
2
mV
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
54 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol AM Parameter AM suppression Conditions referenced to 27 kHz FM deviation; 50 s de-emphasis; AM: f = 1 kHz; m = 54 % fripple = 70 Hz; see Figure 11 Min 35 Typ 46 Max Unit dB
PSRR Audio amplifier
power supply ripple rejection
14
20
-
dB
Audio output; pin AUD RO VO RL CL Vo(AF)(RMS) output resistance output voltage load resistance load capacitance RMS AF output voltage 25 kHz FM deviation; 75 s de-emphasis; see Table 28 0 dB -6 dB -12 dB -18 dB AM; m = 54 %; see Table 28 0 dB -6 dB f-3dB(AF)u f-3dB(AF)l mute Vjmp upper AF cut-off frequency lower AF cut-off frequency mute attenuation W3[2] = 0 (without de-emphasis) W3[2] = 0 (without de-emphasis) of AF signal
[19] [3]
2.0 10 100 -
2.4 -
300 2.7 1
V k k nF
AC-coupled DC-coupled
[3] [3] [3]
400 -
500 250 125 62.5
600 -
mV mV mV mV
400 70 -
500 250 150 20 50
600 150
mV mV kHz Hz dB mV
[20]
jump voltage difference (DC) switching AF output to mute state or vice versa; activated by digital acquisition help W3[6] = 1 or via W3[5] power supply ripple rejection fripple = 70 Hz; see Figure 11
PSRR
14
20
-
dB
De-emphasis network; pin CDEEM VO output voltage 2.4 V
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
55 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol RO Parameter output resistance Conditions W3[3:2] = 11 (50 s de-emphasis) W3[3:2] = 01 (75 s de-emphasis) VAF(RMS) RMS AF voltage fAF = 400 Hz; Vo(AF) = 500 mV (RMS); 0 dB attenuation Min 8.5 13 Typ 170 Max 14 21 Unit k k mV
AF decoupling
Pin CAF1
Vdec decoupling voltage (DC) fFMPLL = 4.5 MHz fFMPLL = 5.5 MHz fFMPLL = 6.0 MHz fFMPLL = 6.5 MHz fFMPLL = 10.7 MHz IL Io(max) leakage current maximum output current output voltage operation[21][22] first sound carrier weighted signal-to-noise ratio PC / SC1 > 40 dB at pins IF1A and IF1B or IF2A and IF2B; 27 kHz FM deviation; BP off; "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) 45 45 43 50 50 47 dB dB dB VAUD < 50 mV (p-p); 0 dB attenuation sink or source 1.5 1.5 1.5 1.5 1.5 1.15 1.9 2.2 2.35 2.5 2.4 1.5 2.4 3.3 3.3 3.3 3.3 3.3 25 1.85 V V V V V nA A V
Pin CAF2
VO FM
Single reference QSS AF performance; pin AUD[23] (S/N)w(SC1)
45
50
-
dB
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
56 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol (S/N)w(SC1) Parameter first sound carrier weighted signal-to-noise ratio Conditions PC / SC1 > 40 dB at pins IF1A and IF1B or IF2A and IF2B; 27 kHz FM deviation; BP off; "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz (S/N)w(SC2) second sound carrier with external reference weighted signal-to-noise ratio FM demodulator; PC / SC2 > 40 dB at pins IF1A and IF1B or IF2A and IF2B; 27 kHz (54 % FM deviation); BP off; "ITU-R BS.468-4" black picture white picture 6 kHz sine wave (black-to-white modulation) 250 kHz square wave (black-to-white modulation) sound carrier subharmonics; f = 2.75 MHz 3 kHz sound carrier subharmonics; f = 2.87 MHz 3 kHz 48 46 42 55 51 46 dB dB dB 53 50 44 58 53 48 dB dB dB Min Typ Max Unit Single reference QSS AF performance with external FM demodulator connected to OUT1A and OUT1B[24]
40
45
-
dB
45
51
-
dB
46
52
-
dB
29
34
-
dB
44
50
-
dB
45
51
-
dB
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
57 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol AM operation L standard; pin AUD Vo(AF)(RMS) THD BAF(-3dB) (S/N)w(AF) RMS AF output voltage total harmonic distortion -3 dB AF bandwidth AF weighted signal-to-noise ratio 54 % modulation 54 % modulation; BP on; see Figure 33 400 12 500 0.5 18 42 50 40 600 1.0 mV % kHz dB dB dB Parameter Conditions Min Typ Max Unit
"ITU-R BS.468-4"
BP on BP off composite IF; VIF modulation = color bar; "ITU-R BS.468-4"; BP on
[3]
38 44 -
Reference frequency General fref VOPTXTAL Ri Rrsn(xtal) Cpull Rswoff(OPTXTAL) reference frequency voltage on pin OPTXTAL (DC) input resistance crystal resonance resistance pull capacitance switch-off resistance on pin OPTXTAL to switch off crystal input by external resistor wired between pin OPTXTAL and GND Rswoff(OPTXTAL) = 0.22 k Rswoff(OPTXTAL) = 3.3 k Reference frequency input from external source; pin OPTXTAL VOPTXTAL Ri Vref(RMS) RO Cdec voltage on pin OPTXTAL (DC) input resistance RMS reference voltage output resistance decoupling capacitance of external reference signal source to external reference signal source pin open-circuit
[3] [3] [26] [25]
2.3
4 2.6 2 -
2.9 200 4.7
MHz V k pF k
Reference frequency generation with crystal; pin OPTXTAL pin open-circuit
[3]
0.22
Iswoff
switch-off current
2.3
[3]
500 2.6 2 2 100
1600 2.9 400 4.7 -
A A V k mV k pF
pin open-circuit
80 22
[3]
Reference frequency input from external source; W7[7] = 0; pin FREF VFREF Ri
TDA9897_TDA9898_3
voltage on pin FREF (DC) input resistance
2.2 50
2.5 -
2.8 -
V k
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
58 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol fref Vref(RMS) RO Parameter reference frequency RMS reference voltage output resistance see Figure 34 of external reference signal source; AC-coupled to external reference signal source to switch off reference signal input by external resistor wired between pin FREF and GND Rswoff(FREF) = 3.9 k Rswoff(FREF) = 22 k I2C-bus VADRSEL transceiver[27] voltage on pin ADRSEL (DC) pin open-circuit for address select MAD1; pin connected to GND MAD3; pin connected to GND via RADRSEL MAD4; pin connected to VP via RADRSEL MAD2; pin connected to VP Ri RADRSEL I2C-bus VBVS Isink(I) Isource(I) VI input resistance resistance on pin ADRSEL voltage on pin BVS (DC) input sink current input source current input voltage pin open-circuit pin connected to VP pin connected to GND VCC(I2C-bus) = 5.0 V; pin connected to VP VCC(I2C-bus) = 3.3 V; pin open-circuit VCC(I2C-bus) = 2.5 V; pin connected to GND voltage select; pin BVS 0.88VP 0.46VP 0 0.52VP 10 60 VP 0.58VP 0.12VP V A A V V V
[3]
Conditions
[25]
Min 15 -
Typ 4 150 -
Max 500 4.7
Unit MHz mV k
Cdec Rswoff(FREF)
decoupling capacitance switch-off resistance on pin FREF
22 3.9
100 -
27
pF k
Iswoff
switch-off current
-
75
100 -
A A
Address select; pin ADRSEL 0 0.12VP 0.66VP 0.96VP 42.3 0.5VP 35 47 0.04VP 0.30VP 0.86VP VP 51.7 V V V V V k k
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
59 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 53. Characteristics ...continued VP = 5 V; Tamb = 25 C; see Table 25 for input frequencies; B/G standard is used for the specification (fPC = 38.375 MHz; fSC = 32.875 MHz; PC / SC = 13 dB; fAF = 400 Hz); input level Vi(IF) = 10 mV (RMS) (sync level for B/G; peak white level for L); IF input from 50 via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for B/G is 10 % and for L is 3 %; video signal in accordance with "ITU-T J.63 line 17 and line 330" or "NTC-7 Composite"; internal Nyquist slope switched on (W7[0] = 0); not dual mode; measurements taken in test circuit of Figure 50 and Figure 51; unless otherwise specified. Symbol I2C-bus VIH Parameter transceiver; pins SCL and SDA[28] VCC(I2C-bus) = 5.0 V VCC(I2C-bus) = 3.3 V VCC(I2C-bus) = 2.5 V VIL LOW-level input voltage VCC(I2C-bus) = 5.0 V VCC(I2C-bus) = 3.3 V VCC(I2C-bus) = 2.5 V IIH IIL VOL fSCL
[1] [2] [3] [4] [5]
[29] [30] [30] [29] [30] [30]
Conditions
Min 0.6VP 2.3 1.75 -0.3 -0.3 -0.3 -10 -10
Typ -
Max VP VP VP +0.3VP +1.0 +0.75 +10 +10 0.4 400
Unit V V V V V V A A V kHz
HIGH-level input voltage
HIGH-level input current LOW-level input current LOW-level output voltage SCL clock frequency
Values of video and sound parameters can be decreased at VP = 4.5 V. Condition for secure POR is a rise or fall time greater than 2 s.
IOL = 3 mA; for data transmission (SDA)
0
This parameter is not tested during the production and is only given as application information for designing the receiver circuit. Level headroom for input level jumps during gain control setting. BLF(-3dB) = 100 kHz (damping factor d = 1.9; calculated with sync level within gain control range). Calculation of the VIF PLL filter can be done by use of the following formula:
1 B LF ( -3dB ) = ----- O K D R , valid for d 1.2 -K 2 1 d = -- R K O K D C , 2
where:
Hz A rad KO is the VCO steepness ------- or 2 ----- ; KD is the phase detector steepness ------- ; sV V rad
R is the loop filter serial resistor (); C is the loop filter serial capacitor (F); BLF(-3dB) is the -3 dB LF bandwidth (Hz); d is the damping factor. [6] [7] [8] [9] The VCO frequency offset related to the PC frequency is set to 1 MHz with white picture video modulation. AC load; CL < 20 pF and RL > 1 k. The sound carrier frequencies (depending on TV standard) are attenuated by the integrated sound carrier traps. Condition: luminance range (5 steps) from 0 % to 100 %. Measurement value is based on 4 of 5 steps. Measurement using 200 kHz high-pass filter, 5 MHz low-pass filter and subcarrier notch filter ("ITU-T J.64").
[10] Modulation VSB; sound carrier off; fvideo > 0.5 MHz. [11] Sound carrier on; fvideo = 10 kHz to 10 MHz. [12] The sound carrier trap can be bypassed by setting the I2C-bus bit W2[0] to logic 0; see Table 24. In this way the full composite video spectrum appears at pin CVBS. The video amplitude is reduced to 1.1 V (p-p). [13] Measurement condition: with transformer, transmitter pre-correction on; reference is at 1 MHz. [14] The response time is valid for a VIF input level range from 200 V to 70 mV. [15] See Figure 19 to smooth current pulses.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
60 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
[16] To match the AFC output signal to different tuning systems a current output is provided. The test circuit is given in Figure 19. The AFC steepness can be changed by resistors R1 and R2. [17] The AFC value of the VIF and RIF frequency is generated by using digital counting methods. The used counter resolution is provided with an uncertainty of 1 bit corresponding to 25 kHz. This uncertainty of 25 kHz has to be added to the frequency accuracy parameter. [18] Measured with an FM deviation of 25 kHz and the typical AF output voltage of 500 mV (RMS). The audio signal processing stage provides headroom of 6 dB with THD < 1.5 %. The I2C-bus bits W3[0] and W3[1] control the AF output signal amplitude from 0 dB to -18 dB in steps of -6 dB. Reducing the audio gain for handling a frequency deviation of more than 55 kHz avoids AF output signal clipping. [19] Amplitude response depends on dimensioning of FM PLL loop filter. [20] The lower AF cut-off frequency depends on the value of the capacitor at pin CAF1. A value of CAF1 = 470 nF leads to f-3dB(AF)l 20 Hz and CAF1 = 220 nF leads to f-3dB(AF)l 40 Hz. [21] For all signal-to-noise measurements the used VIF modulator has to meet the following specifications: a) Incidental phase modulation for black-to-white jump less than 0.5 degrees. b) QSS AF performance, measured with the television demodulator AMF2 (audio output, weighted signal-to-noise ratio) better than 60 dB (at deviation 27 kHz) for 6 kHz sine wave black-to-white video modulation. c) Picture-to-sound carrier ratio PC / SC1 = 13 dB (transmitter). [22] The PC / SC ratio is calculated as the addition of TV transmitter PC / SC1 ratio and SAW filter PC / SC1 ratio. This PC / SC ratio is necessary to achieve the weighted signal-to-noise values as noted. A different PC / SC ratio will change these values. [23] Measurement condition is SC1 / SC2 7 dB. [24] The differential QSS signal output on pins OUT1A and OUT1B is analyzed by a test demodulator TDA9820. The signal-to-noise ratio of this device is better than 60 dB. The measurement is related to an FM deviation of 27 kHz and in accordance with "ITU-R BS.468-4". [25] The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum FM deviation, sound trap frequency, LIF band-pass cut-off frequency and ZIF low-pass cut-off frequency as well as the accuracy of the synthesizer. [26] The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal. [27] The AC characteristics are in accordance with the I2C-bus specification for fast mode (maximum clock frequency is 400 kHz). Information about the I2C-bus can be found in the brochure "The I2C-bus and how to use it" (order number 9398 393 40011). [28] The SDA and SCL lines will not be pulled down if VP is switched off. [29] The threshold is dependent on VP. [30] The threshold is independent of VP.
Table 54. 210 410 130 210 Table 55. Symbol fPC fSC1 fSC2
Examples to the FM PLL filter Cs (nF) 2.2 2.2 2.2 2.2 Cpar (pF) 100 47 470 47 Rs (k) 8.2 5.6 5.6 8.2 Comment recommended for single-carrier-sound, FM narrow recommended for single-carrier-sound, FM wide recommended for two-carrier-sound, FM narrow used for test circuit
BLF(-3dB) (kHz)
Input frequencies and carrier ratios (examples) Parameter picture carrier frequency sound carrier frequency 1 sound carrier frequency 2 B/G standard M/N standard L standard L-accent standard Unit 38.375 32.825 32.583 13 20 38.375 33.825 7 38.375 31.825 10 33.625 40.125 10 MHz MHz MHz dB dB
PC / SC1 picture to first sound carrier ratio PC / SC2 picture to second sound carrier ratio
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
61 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
trap bypass mode normal mode 2.72 V 2.6 V 3.41 V 3.20 V zero carrier level white level
1.83 V
1.80 V
black level
1.5 V
1.20 V
sync level
mhc115
Fig 10. Typical video signal levels on output pin CVBS (sound carrier off)
V = VP + Vripple
TDA9897 TDA9898
VP (V) 5.050 5.000 4.950
t (s)
001aae391
Fig 11. Ripple rejection condition
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
62 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 Vmonitor(VIFAGC) (V) 4
001aad353
5 VTAGC (V) 4
3
3
2
(1) (2) (3) (4)
2
1
1
0 30 50 70 90
0 110 130 Vi(VIF) (dBV)
(1) VIF AGC. (2) TAGC; W10 = 00h. (3) TAGC; W10 = 10h. (4) TAGC; W10 = 1Fh.
Fig 12. Typical VIF monitor and TAGC characteristic
100 Vi(IF) (dBV) 90
001aaf640
80
70
60
Fig 13. Typical tuner takeover point as a function of I2C-bus register W9 or W10
TDA9897_TDA9898_3
Product data sheet
0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 Integral TAGC (W9); step width: 1.3 dBV. IF based TAGC (W10). bit pattern W9[4:0] or W10[4:0]
(c) NXP B.V. 2008. All rights reserved.
50
Rev. 03 -- 11 January 2008
63 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
100 Vi(IF) (dBV) 90
008aaa034
80
70
(1)
60 0 5 10 15 20 25 RTOP2 (k)
(1) IF based TAGC (TOP2).
Fig 14. Typical tuner takeover point as a function of resistor RTOP2
5 VAGC(FM) (V) 4
001aad356
5 VAGC(SIF) (V) 4
001aad357
3
3
2
2
(1) (2)
1
1
0 40 60 80 100 120 Vi(EXTFMI) (dBV)
0 20 40 60 80 100 120 Vi(SIF) (dBV)
(1) AM. (2) FM.
Fig 15. Typical FM AGC characteristic measured at pin MPP2
Fig 16. Typical SIF AGC characteristic measured at pin MPP2
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
64 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
250 fAFC(VIF)(5) (kHz) 150
(1)
008aaa035
250 IAFC(6) (A) 150
50 bit AFCWIN (R1[7]) = 1 0 -50
(3) (2)
50 0 -50
-150
(4)
-150
-250 36.375
36.875
37.375
37.875
38.375
38.875
39.375
-250 39.875 40.375 fVIF (MHz)
(1) VIF AFC via I2C-bus; accuracy is 1 digit. (2) Bit AFCWIN via I2C-bus (VCO is in 1.6 MHz window) for all standards except M/N standard. (3) Bit AFCWIN via I2C-bus (VCO is in 0.8 MHz window) for M/N standard. (4) VIF AFC average current. (5) Reading via I2C-bus. (6) Average; RC network at pin MPP2.
Fig 17. Typical analog and digital AFC characteristic for VIF
250 fAFC(RIF)(4) (kHz) 150
(1)
001aad443
250 IAFC(5) (A) 150
(2)
50 0 -50
50 0 -50
-150 AFC undefined 5.2 bit CARRDET (R1[5]) = 1 5.4 5.6
(3)
-150 AFC undefined 5.8 fRIF (MHz)
-250 5.0
-250 6.0
Characteristics of digital and analog radio AFC is mirrored with respect to center frequency when lower sideband is used (W2[3] = 0). (1) RIF AFC via I2C-bus. (2) FM carrier detection via I2C-bus. (3) RIF AFC average current. (4) Reading via I2C-bus. (5) Average; RC network at pin MPP2.
Fig 18. Typical analog and digital AFC characteristic for RIF
TDA9897_TDA9898_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
65 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
VP
R1 22 k
IAFC MPP2
TDA9897 TDA9898
R2 22 k
100 nF
001aae392
Fig 19. RC network for measurement of analog AFC characteristic
60 S/N (dB) 50
(2)
001aad660
(1)
40
30 50 60 70 80 90 100 Vi(VIF) (dBV)
(1) B/G standard; weighted video S/N; using 50 % grey picture. (2) M/N standard; unweighted video S/N; using 50 IRE grey picture.
Fig 20. Typical signal-to-noise ratio as a function of VIF input voltage
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
66 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2
001aad487
(1) (3)
(2)
3
4
5 f (MHz)
6
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 21. Typical amplitude frequency response for sound trap at M/N standard (including Korea)
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5
(1)
001aad365
(3)
(2)
6 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 22. Typical group delay response for sound trap at M/N standard
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
67 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3
001aad488
(1)
(2)
(3)
4
5
6
7 f (MHz)
8
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 23. Typical amplitude frequency response for sound trap at B/G standard
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7
(1) (3)
001aad361
(2)
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 24. Typical group delay response for sound trap at B/G standard
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
68 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3
001aad489
(1)
(2)
(3)
4
5
6
7 f (MHz)
8
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 25. Typical amplitude frequency response for sound trap at I standard
250 200 td(grp) (ns) 150 100
(1)
001aad363
50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7 f (MHz) 8
(3)
(2)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 26. Typical group delay response for sound trap at I standard
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
69 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3
001aaf551
(1)
(2)
(3)
4
5
6
7 f (MHz)
8
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 27. Typical amplitude frequency response for sound trap at D/K standard
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7
(1)
001aaf552
(3)
(2)
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 28. Typical group delay response for sound trap at D/K standard
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
70 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
5 resp(f) 0 (dB) -5 -10 -15 -20 -25 -30 -35 -40 -45 0 1 2 3
001aad491
(1)
(2)
(3)
4
5
6
7 f (MHz)
8
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap amplitude frequency response.
Fig 29. Typical amplitude frequency response for sound trap at L standard
250 200 td(grp) (ns) 150 100 50 0 -50 -100 -150 -200 -250 0 1 2 3 4 5 6 7
(1) (3)
001aad364
(2)
8 f (MHz)
(1) Minimum requirements upper limit. (2) Minimum requirements lower limit. (3) Typical trap group delay response.
Fig 30. Typical group delay response for sound trap at L standard
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
71 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
10 resp(f) (dB) 0
(1) (5) (3) (2) (4)
001aaf579
-10
(7) (6)
-20
-30
-40
-50 -3.0
-2.0
-1.0
0
1.0
2.0
f - fc (MHz)
3.0
(1) Center frequency. (2) Minimum upper cut-off frequency. (3) Minimum lower cut-off frequency. (4) Maximum upper cut-off frequency. (5) Maximum lower cut-off frequency. (6) Minimum upper stop-band attenuation. (7) Minimum lower stop-band attenuation.
Fig 31. Typical sound BP amplitude frequency response at TV mode, normalized to BP center frequency
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
72 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
10 resp(f) (dB) 0
(1) (5) (3) (2) (4)
001aaf578
-10
(7) (6)
-20
-30
-40
-50 -3.0
-2.0
-1.0
0
1.0
2.0
f - fc (MHz)
3.0
(1) Center frequency. (2) Minimum upper cut-off frequency. (3) Minimum lower cut-off frequency. (4) Maximum upper cut-off frequency. (5) Maximum lower cut-off frequency. (6) Minimum upper stop-band attenuation. (7) Minimum lower stop-band attenuation.
Fig 32. Typical sound BP amplitude frequency response at radio 10.7 mode, normalized to BP center frequency
2.0 THD (%) 1.5
001aad359
1.0
0.5
0 10-2
10-1
1
10 fAF (kHz)
102
Fig 33. Typical total harmonic distortion as a function of audio frequency at AM standard
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
73 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
55 (S/N)w (dB) 45
001aaf468
35
25 0 50 100 150 200 Vi(FREF)(RMS) (mV)
Reference frequency input signal taken from external quartz circuit.
Fig 34. Weighted FM audio S/N versus reference frequency input level using radio mode
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
74 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
120 antenna input level (dBV) 100
001aaf639
1 IF signal RMS values (V) 10-1
(5) (4)
(2)
(3)
(6)
80
RF gain control range IF gain control range limited by TOP adjustment
10-2 IF gain control range 10-3
60
40
10-4
(1)
20
10-5
(7)
output
output
output
output
tuner TD1716
band-pass X3450L
VIF amplifier
demodulator IF demodulator, TDA989x
video amplifier
Video signal related peak-to-peak levels are divided by factor 22 in order to conform with the RMS value scale of the secondary y-axis, but disregarding the none sine wave signal content. (1) Signal levels for -1 dB video output level using maximum RF gain and maximum IF gain. (2) Signal levels for +1 dB video output level using minimum IF gain. (3) Signal levels for TOP-adjusted tuner output level using maximum RF gain and adjustment-related minimum IF gain. (4) Signal levels for TOP-adjusted tuner output level using minimum RF gain and adjustment-related minimum IF gain. (5) TOP-adjusted tuner output level. (6) TOP-adjusted VIF amplifier input level. (7) Minimum antenna input level at -1 dB video level.
Fig 35. Front-end level diagram
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
output
input
input
input
input
input
0
10-6
75 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
12.2 Digital TV signal processing
Table 56. Characteristics VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol VI Ri(dif) Ci(dif) GIF(cr) VO Ibias(int) Isink(o)(max) Isource(o)(max) RO Parameter input voltage differential input resistance differential input capacitance control range IF gain output voltage internal bias current (DC) maximum output sink current maximum output source current output resistance pin open-circuit for emitter-follower DC and AC; see Figure 36 DC and AC; see Figure 36 differential; output active output inactive; internal resistance to GND Vi(IF)(RMS) RMS IF input voltage minimum input sine wave level for nominal output level maximum input sine wave level for nominal output level permissible overload Direct IF; pins OUT2A and OUT2B GIF(max) Vo(dif)(p-p) maximum IF gain peak-to-peak differential output voltage output peak-to-peak level to input RMS level ratio between pin OUT2A and pin OUT2B W4[7] = 0 W4[7] = 1 C/N carrier-to-noise ratio at fo = 33.4 MHz; see Figure 37 Vi(IF) = 10 mV (RMS) Vi(IF) = 0.5 mV (RMS) IM intermodulation suppression input signals: fi = 47.0 MHz and 57.5 MHz; output signals: fo = 36.5 MHz or 68.0 MHz; see Figure 38 W4[7] = 0 W4[7] = 1
TDA9897_TDA9898_3
Conditions
Min 1.8
[2]
Typ 1.93 2 3 66 2.0 2.5 1.7 800 70 170 83
Max 2.2 2.2 50 100 320 -
Unit V k pF dB V mA mA mA V mV mV dB
IF amplifier; pins IF3A and IF3B or IF1A and IF1B or IF2A and IF2B 60 1.8 2.0
[3]
[2]
[2]
DTV differential output; pins OUT1A, OUT1B, OUT2A and OUT2B
1.4 6.0 130
[3]
[2] [2]
[2]
-
[2]
[4]
[2][5][6]
1.0 0.50
1.1 0.55
V V
115 90
[2]
124 104
-
dBc/Hz dBc/Hz
40 40
-
-
dB dB
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
76 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol fIF(-1dB)l f-3dB(IF)u PSRR Parameter lower -1 dB IF cut-off frequency upper IF cut-off frequency power supply ripple rejection W4[7] = 0 W4[7] = 1 residual spurious at nominal differential output voltage dependent on power supply ripple fripple = 70 Hz fripple = 20 kHz GIF(max) fsynth Vo(dif)(p-p) maximum IF gain output peak-to-peak level to input RMS level ratio W4[7] = 0 W4[7] = 1 residual spurious at nominal differential output voltage dependent on power supply ripple fripple = 70 Hz fripple = 20 kHz Low IF output signal; pins OUT1A and OUT1B ripple(pb)LIF low IF pass-band ripple 6 MHz bandwidth 7 MHz bandwidth 8 MHz bandwidth B-3dB -3 dB bandwidth BP off 6 MHz bandwidth 7 MHz bandwidth 8 MHz bandwidth stpb stop-band attenuation 6 MHz band; f = 11.75 MHz 6 MHz band; f = 20 MHz 7 MHz band; f = 13.75 MHz 7 MHz band; f = 20 MHz 8 MHz band; f = 15.75 MHz 8 MHz band; f = 20 MHz
[4] [4] [4] [4] [2]
Conditions
[2]
Min 60 60
Typ 7 -
Max -
Unit MHz MHz MHz
[4] [7] [2]
[4] [4] [2]
60 60 89 2 1
-
dB dB dB MHz V V
Low or zero IF output signal; pins OUT1A and OUT1B or pins OUT2A and OUT2B; differential
synthesizer frequency see Table 35 and Table 36 peak-to-peak differential output voltage power supply ripple rejection
-
PSRR
11 30 28 30 28 30 28
50 30 15 7.8 8.8 9.8 40 35 40 35 40 35
2.7 2.7 2.7 -
dB dB dB dB dB MHz MHz MHz MHz dB dB dB dB dB dB
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
77 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol td(grp) Parameter group delay time variation Conditions from 1 MHz to 2 MHz from 2 MHz to end of band with a bandwidth of 6 MHz 7 MHz 8 MHz image image rejection -10 MHz to 0 MHz BP on BP off C/N carrier-to-noise ratio at fo = 4.9 MHz; see Figure 37 Vi(IF) = 10 mV (RMS) Vi(IF) = 0.5 mV (RMS) H(ib) in-band harmonics suppression low IF = multiple of 1.31 MHz; fi = fsynth + 1.31 MHz; see Figure 41 W4[7] = 0 W4[7] = 1 IM intermodulation suppression input signals: fi = fsynth + 4.7 MHz and fsynth + 5.3 MHz; output signals: fo = 4.1 MHz or 5.9 MHz; see Figure 40 W4[7] = 0 W4[7] = 1 sp(ib) in-band spurious suppression single-ended AC load; RL = 1 k; CL = 5 pF; 1 MHz to end of band; BP on single-ended AC load; RL = 1 k; CL = 5 pF; BP on 3.0 MHz bandwidth 3.5 MHz bandwidth 4.0 MHz bandwidth B-3dB -3 dB bandwidth BP off 3.0 MHz bandwidth 3.5 MHz bandwidth 4.0 MHz bandwidth
[4] [4] [4] [4] [2] [2] [2] [2][5][6] [2] [2]
Min -
Typ 90
Max 200
Unit ns
30 24
90 90 90 34 28
160 160 160 -
ns ns ns dB dB
112 90
118 104
-
dBc/Hz dBc/Hz
40 40
-
-
dB dB
40 40 50
-
-
dB dB dB
sp(ob)
out-band spurious suppression zero IF pass-band ripple
[2]
50
-
-
dB
Zero IF output signal; pins OUT1A and OUT1B or pins OUT2A and OUT2B ripple(pb)ZIF 11 15 3.7 4.2 4.7 1.8 1.8 1.8 dB dB dB MHz MHz MHz MHz
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
78 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol stpb Parameter Conditions 3.5 MHz band; f = 9.25 MHz 4.0 MHz band; f = 10.75 MHz any band; f = 15 MHz td(grp) group delay time variation from 0 MHz to end of band with a bandwidth of 3.0 MHz 3.5 MHz 4.0 MHz C/N carrier-to-noise ratio at fo = 1.9 MHz; see Figure 37 Vi(IF) = 10 mV (RMS) Vi(IF) = 0.5 mV (RMS) IM intermodulation suppression input signals: fi = fsynth + 1.7 MHz and fsynth + 2.3 MHz; output signals: fo = 1.1 MHz or 2.9 MHz; see Figure 39 0.437 MHz to end of band; BP on BP on mismatch between I and Q channel mismatch between I and Q channel
[2] [2][4] [2][5][6] [2]
Min 30 30 30 28
Typ 40 40 40 35
Max -
Unit dB dB dB dB
stop-band attenuation 3.0 MHz band; f = 7.75 MHz
-
60 50 45
100 100 100
ns ns ns
112 87 40
121 101 -
-
dBc/Hz dBc/Hz dB
sp(ib) sp(ob) G
in-band spurious suppression out-band spurious suppression phase difference gain mismatch
40 50 -
-
6 2
dB dB deg dB
[2][4]
[2]
IF AGC control; pin AGCDIN Isink(i)(max) Vi(max) VAGCDIN GIF/VAGCDIN maximum input sink current maximum input voltage voltage on pin AGCDIN change of IF gain with VAGCDIN = 0.8 V to 2.2 V voltage on pin AGCDIN 0 -45 2 VP 3 A V V dB/V
[2]
[2]
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
79 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Tuner AGC; pin TAGC Integral TAGC loop mode (W6[7:6] = 10); TAGC is current output; unmodulated IF Vi(IF)(RMS) RMS IF input voltage at starting point of tuner AGC takeover; Isink(TAGC) = 100 A W9[4:0] = 0 0000 W9[4:0] = 1 0000 W9[4:0] = 1 1111 acc(set)TOP Isource TOP setting accuracy source current TAGC charge current normal mode fast mode activated by internal level detector Isink sink current TAGC discharge current; VTAGC = 1 V Isink(TAGC) = 100 A; W9[4:0] = 1 0000
[2]
-2 0.20 7 400 -
57.9 78.7 98.2 0.27 10 500 -
+2 0.34 13 600 0.02
dBV dBV dBV dB A A A dB/K
acc(set)TOP/T TOP setting accuracy variation with temperature RL Vsat(u) Vsat(l) th(fast)AGC load resistance upper saturation voltage lower saturation voltage AGC fast mode threshold
[2]
50 VP - 0.3 6
8
0.3 10
M V V dB
pin operating as current output pin operating as current output activated by internal fast AGC detector; I2C-bus setting corresponds to W9[4:0] = 1 0000 before activating; Vi(IF) below th(fast)AGC
[2]
[2]
[2]
td
delay time
[2]
40
60
80
ms
Filter synthesizer PLL; pin LFSYN1 VLFSYN1 KO KD Isink(o)PD(max) voltage on pin LFSYN1 VCO steepness phase detector steepness maximum phase detector output sink current maximum phase detector output source current fVCO / VLFSYN1 ILFSYN1 / VCO 1.0 3.75 9 3.5 65 V MHz/V A/rad A
Isource(o)PD(max)
-
-
65
A
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
80 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol VLFSYN2 KO KD Parameter voltage on pin LFSYN2 VCO steepness phase detector steepness fVCO / VLFSYN2 ILFSYN2 / VCO; see Table 57; fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz Io(PD) phase detector output sink or source; current fVCO selection: 22 MHz to 29.5 MHz 30 MHz to 37.5 MHz 38 MHz to 45.5 MHz 46 MHz to 53.5 MHz 57 MHz n(synth) synthesizer phase noise fsynth = 31 MHz; fIF = 36 MHz at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz fsynth = 40 MHz; fIF = 44 MHz; external 4 MHz reference signal of 265 mV (RMS) and phase noise better than 120 dBc/Hz; see Figure 46 at 1 kHz at 10 kHz at 100 kHz at 1.4 MHz sp IL spurious suppression leakage current multiple of f = 500 kHz synthesizer spurious performance > 50 dBc
[2] [2] [2] [2] [2] [2] [2] [2] [2] [2]
Conditions
Min 1 -
Typ 31
Max 3 -
Unit V MHz/V
Conversion synthesizer PLL; pin LFSYN2
-
32 38 47 61 61
-
A/rad A/rad A/rad A/rad A/rad
-
200 238 294 384 384
-
A A A A A
89 89 98 115
99 99 102 119
-
dBc/Hz dBc/Hz dBc/Hz dBc/Hz
89 89 96 115 50 -
96 100 100 118 -
10
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc nA
Reference frequency General fref
TDA9897_TDA9898_3
reference frequency
[8]
-
4
-
MHz
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
81 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 56. Characteristics ...continued VP = 5 V[1]; Tamb = 25 C; 8 MHz system; see Table 34 and Table 35; CW test input signal is used for specification; Vi(IF) = 10 mV (RMS); fIF = 36 MHz for low IF output of 5 MHz; IF input from 50 via broadband transformer 1 : 1; gain controlled amplifier adjusted to typical specified output level; measurements taken in test circuit of Figure 50 and Figure 51 with 4 MHz crystal oscillator reference; unless otherwise specified. Symbol VOPTXTAL Ri Rrsn(xtal) Cpull Rswoff(OPTXTAL) Parameter voltage on pin OPTXTAL (DC) input resistance crystal resonance resistance pull capacitance switch-off resistance on pin OPTXTAL to switch off crystal input by external resistor wired between pin OPTXTAL and GND Rswoff(OPTXTAL) = 0.22 k Rswoff(OPTXTAL) = 3.3 k Reference frequency input from external source; pin OPTXTAL VOPTXTAL Ri Vref(RMS) RO Cdec voltage on pin OPTXTAL (DC) input resistance RMS reference voltage output resistance decoupling capacitance voltage on pin FREF (DC) input resistance reference frequency RMS reference voltage output resistance decoupling capacitance switch-off resistance on pin FREF see Figure 46 of external reference signal source; AC-coupled to external reference signal source to switch off reference signal input by external resistor wired between pin FREF and GND Rswoff(FREF) = 3.9 k Rswoff(FREF) = 22 k
[1] [2] Some parameters can be decreased at VP = 4.5 V. This parameter is not tested during production and is only given as application information.
(c) NXP B.V. 2008. All rights reserved.
Conditions pin open-circuit
[2]
Min 2.3 [9]
Typ 2.6 2 -
Max 2.9 200 4.7
Unit V k pF k
Reference frequency generation with crystal; pin OPTXTAL
0.22
Iswoff
switch-off current
2.3
[2]
500 2.6 2 2 100
1600 2.9 400 4.7 -
A A V k mV k pF
pin open-circuit
80
of external reference signal source to external reference signal source pin open-circuit
[2]
22
[2]
Reference frequency input from external source; W7[7] = 0; pin FREF VFREF Ri fref Vref(RMS) RO Cdec Rswoff(FREF) 2.2
[2] [8]
2.5 4 150 100 -
2.8 500 4.7 27
V k MHz mV k pF k
50 15 22 3.9
Iswoff
switch-off current
-
75
100 -
A A
TDA9897_TDA9898_3
Product data sheet
Rev. 03 -- 11 January 2008
82 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
[3] [4] [5] [6] [7] [8]
Output current can be increased by application of single-ended resistor from each output pin to GND. Recommended resistor value is minimum 1 k. With single-ended load for fIF < 45 MHz RL 1 k and CL 5 pF to ground and for fIF = 45 MHz to 60 MHz RL = 1 k and CL 3 pF to ground. Noise level is measured without input signal but AGC adjusted corresponding to the given input level. Set with AGC nominal output voltage as reference. For C/N measurement switch input signal off. With single-ended load RL 1 k and CL 5 pF to ground. The tolerance of the reference frequency determines the accuracy of VIF AFC, RIF AFC, FM demodulator center frequency, maximum FM deviation, sound trap frequency, LIF band-pass cut-off frequency and ZIF low-pass cut-off frequency as well as the accuracy of the synthesizer. The value of Cpull determines the accuracy of the resonance frequency of the crystal. It depends on the used type of crystal.
[9]
Table 57. fVCO (MHz) 22 to 29.5 30 to 37.5 38 to 45.5 46 to 53.5 57
[1]
Conversion synthesizer PLL; loop filter dimensions[1] RLFSYN2 (k)[2] 1.5 1.8 2.2 2.7 3.3 CLFSYN2 (nF) 4.7 4.7 4.7 4.7 4.7
Calculation of the PLL loop filter by using the following formulae, valid under the condition for the damping factor d 1.2. B LF ( - 3dB ) = ------ D R LFSYN2 and d = -- R LFSYN2 2 ------ D C LFSYN2 with the following -K -K parameters KO = VCO steepness (MHz/V), N = divider ratio: N = ------------------- , KD = phase frequency detector steepness (A/rad), RLFSYN2 = synthesizer loop filter serial resistor (), CLFSYN2 = synthesizer loop filter serial capacitor (F), BLF(-3dB) = -3 dB LF bandwidth (Hz), d = damping factor.
KO N
1 2
KO N
f VCO 0.5 MHz
[2]
If more than one frequency range is used in the application, then the smallest resistor value should be applied.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
83 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
30
(3)
001aah343
CL(dif) (pF) 20
(2)
10
(1)
0 0 1 2 RL(dif) (k) 3
W4[7] = 0; nominal output level (1) Direct IF, fmax = 40 MHz, with single-ended resistors of 1 k to GND. (2) Low IF, fmax = 9 MHz. (3) Zero IF, fmax = 4 MHz.
Fig 36. Maximum differential load figures at OUT1/OUT2
130 C/N (dBc/Hz) 120
001aaf467
110
(1) (2) (3)
100
90
80 30 50 70 90 110 Vi(IF)(RMS) (dBV)
(1) Direct IF. (2) Low IF. (3) Zero IF.
Fig 37. Typical C/N ratio as a function of IF input voltage
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
84 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Vi(IF)(RMS) (dBV) 74
Vo(dif)(p-p) (V) 0.5
(1)
IM
0
0
47
57.5
0 fi (MHz)
0
36.5
47
57.5
68
input signal
output signal
fo (MHz)
008aaa051
(1) 0.25 V for W4[7] = 1.
Fig 38. Direct IF signal conditions for measurement of intermodulation at OUT2
Vi(IF)(RMS) (dBV) 74
Vo(dif)(p-p) (V) 1.0
(1)
IM
0 36 fsynth
37.7
38.3
0 fi (MHz)
0
1.1
1.7
2.3
2.9
input signal
output signal
fo (MHz)
008aaa052
(1) 0.5 V for W4[7] = 1.
Fig 39. Zero IF signal conditions for measurement of intermodulation at OUT1 and OUT2
Vi(IF)(RMS) (dBV) 74
Vo(dif)(p-p) (V) 0.5
(1)
IM
0 36 fsynth
40.7
41.3
0 fi (MHz)
0
4.1
4.7
5.3
5.9
input signal
output signal
fo (MHz)
008aaa053
(1) 0.25 V for W4[7] = 1.
Fig 40. Low IF signal conditions for measurement of intermodulation at OUT1
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
85 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Vi(IF)(RMS) (dBV) 80
Vo(dif)(p-p) (V) 2.0
(1)
H(ib)
0 36 fsynth
37.31 input signal
0 fi (MHz)
0
1.31
2.62
3.93
5.24
6.55
7.86
output signal
fo (MHz)
008aaa054
(1) 1.0 V for W4[7] = 1.
Fig 41. Low IF signal conditions for measurement of harmonics at OUT1
2 resp(f) (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 0 2 4 6 8
(3) (1) (2) (3)
001aad494
td(grp)LIF (ns)
100 0 -100 -200
10
12 f (MHz)
tolerance scheme:
(1) (2) (3)
(1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz.
Fig 42. Detailed low IF amplitude and group delay pass-band tolerance scheme
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
86 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
10 resp(f) (dB) 0 -10 -20 -30 -40
(3)
001aad495
-50 -60 -70 -30 -25 -20 -15
(2) (1)
-10
-5
0 f (MHz)
tolerance scheme:
(1) (2) (3)
(1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz.
Fig 43. Low IF amplitude stop-band tolerance scheme
10 resp(f) (dB) 0 -10 -20 -30 -40 -50 -60 -70
001aad496
(1) (2) (3)
0
5
10
15
20
25 30 f (MHz)
(3)
tolerance scheme:
(1) (2)
(1) Channel bandwidth = 6 MHz. (2) Channel bandwidth = 7 MHz. (3) Channel bandwidth = 8 MHz.
Fig 44. Low IF amplitude pass-band tolerance scheme
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
87 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
100 G(7) (dB) 80
008aaa089
60
(1) (2) (3)
(4) (5) (6)
40
20
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VAGCDIN (V)
(1) 2.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 0, W4[7] = 0). (2) 1.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 0, W4[7] = 1; DIF, W9[7] = 0, W4[7] = 0). (3) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 0, W4[7] = 1). (4) 2.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 1, W4[7] = 0). (5) 1.0 V (p-p) differential output voltage (LIF or ZIF, W9[7] = 1, W4[7] = 1; DIF, W9[7] = 1, W4[7] = 0). (6) 0.5 V (p-p) differential output voltage (DIF, W9[7] = 1, W4[7] = 1). (7) Ratio of output peak-to-peak level to input RMS level.
Fig 45. Typical gain characteristic for AGCDIN control voltage
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
88 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
105 n(synth) (dBc/Hz) 95
001aag285
(1) (2)
(3)
85
75 0 100 200 300 400 500 Vi(FREF)(RMS) (mV)
fsynth = 40 MHz; fIF = 44 MHz (1) f = 100 kHz. (2) f = 10 kHz. (3) f = 1 kHz.
Fig 46. Typical synthesizer phase noise at carrier frequency plus f on LIF output versus input voltage on pin FREF
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
89 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
13. Application information
tuner AGC output 4 MHz reference input
3.3 k(2) CTAGC 220 nF CFREF 100 pF 22 k(1) 4 MHz(3) 470 100 nF
synthesizer trap control loop filter
VP = 5 V synthesizer downconverter loop filter(4)
RLFSYN2 CLFSYN2
analog ground n.c.
22 pF
i.c.
22 pF
n.c. 41 40 39 38 37 36 n.c.
CAF2
48 1
47
46
45
44
43
42
AGC input for DIF (from channel decoder)
n.c.
2
35
3
34
1.5 nF
4
CIFAGC
33
2 V CVBS output BVS
5
470 nF
32
IF(5)
SAW VIF X6872 7 MHz WINDOW
CCTAGC
6
31
AUD
(6)
TDA9898
7 30
(b)
(6)
ZIF Q or 1st DIF (a)
8
390 nF
29
CAF1
SAW VIF X6768 6 MHz WINDOW
9
28
470 nF
10
27
(6)
(b) (a)
(6)
11 MPP1
26
digital LIF or ZIF I or analog 2nd sound IF
12 13 14 15 16 MPP2
220 nF 560 (6) Cpar Cs Cde-em 4.7 nF
25 17 18 19 20 21 22 23 24
digital ground ADRSEL
100 100
BP
330
FM PLL (7) 560 loop filter
Rs
VIF loop filter
external FM input
SDA
SCL
008aaa092
(1) Connect resistor if external reference signal is not used. (2) Connect resistor if crystal is not used. (3) Use of crystal is optional. (4) Application depends on synthesizer frequency; see Table 57. (5) Optional single-ended IF input possible. (6) Optional. (7) See Table 54.
Fig 47. Application diagram of TDA9898
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
90 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
tuner AGC output
4 MHz reference input
3.3 k(2)
synthesizer trap control loop filter
CTAGC 220 nF
CFREF 100 pF
22 k(1)
4 MHz(3)
470 100 nF
VP = 5 V synthesizer downconverter loop filter(4)
RLFSYN2 CLFSYN2
analog ground n.c.
22 pF
i.c.
22 pF
n.c. 41 40 39 38 37 36 n.c.
CAF2
48 1
47
46
45
44
43
42
AGC input for DIF (from channel decoder)
n.c.
2
35
3
34
1.5 nF
4 n.c.
33
2 V CVBS output BVS
5
32
IF(5)
SAW VIF X6872 7 MHz WINDOW
CCTAGC
6
31
AUD
(6)
TDA9897
7 30
(b)
(6)
ZIF Q or 1st DIF (a)
8
390 nF
29
CAF1
SAW VIF X6768 6 MHz WINDOW
9
28
470 nF
10
27
(6)
(b) (a)
(6)
11 MPP1
26
digital LIF or ZIF I or analog 2nd sound IF
12 13 14 15 16 MPP2
220 nF 560 (6) Cpar Cs Cde-em 4.7 nF
25 17 18 19 20 21 22 23 24
digital ground ADRSEL
100 100
BP
330
FM PLL (7) 560 loop filter
Rs
VIF loop filter
external FM input
SDA
SCL
008aaa093
(1) Connect resistor if external reference signal is not used. (2) Connect resistor if crystal is not used. (3) Use of crystal is optional. (4) Application depends on synthesizer frequency; see Table 57. (5) Optional single-ended IF input possible. (6) Optional. (7) See Table 54.
Fig 48. Application diagram of TDA9897
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
91 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
tuner AGC output
4 MHz reference input
3.3 k(2)
synthesizer trap control loop filter
CTAGC 220 nF
CFREF 100 pF
22 k(1)
4 MHz(3)
470 100 nF
VP = 5 V synthesizer downconverter loop filter(4)
RLFSYN2 CLFSYN2
analog ground n.c.
22 pF
i.c.
22 pF
n.c. 41 40 39 38 37 36 n.c.
CAF2
48 1
47
46
45
44
43
42
AGC input for DIF (from channel decoder)
n.c.
2
35
IF
SAW SIF X7550
3
34
1.5 nF
4 n.c.
33
2 V CVBS output BVS
5
32
SAW VIF M1980 NYQUIST SLOPE
CCTAGC
6
31
AUD
(6)
TDA9897
7 30
(b)
(6)
ZIF Q or 1st DIF (a)
8
390 nF (5)
29
CAF1
9
28
470 nF
(6)
(5)
10
27
(6)
(b) (a)
(6)
11 MPP1
26
digital LIF or ZIF I or analog 2nd sound IF
12 13 14 15 16 MPP2
220 nF 560 (6) Cpar Cs Cde-em 4.7 nF
25 17 18 19 20 21 22 23 24
digital ground ADRSEL
100 100
BP
1 nF 330
FM PLL (7) 560 loop filter
Rs
VIF loop filter
external FM input
SDA
SCL
008aaa094
(1) Connect resistor if external reference signal is not used. (2) Connect resistor if crystal is not used. (3) Use of crystal is optional. (4) Application depends on synthesizer frequency; see Table 57. (5) Value depends on application. (6) Optional. (7) See Table 54.
Fig 49. Application diagram of TDA9897 using SAW filter with Nyquist slope
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
92 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
14. Test information
tuner AGC output 4 MHz reference input
3.3 k(2) CTAGC 100 nF CFREF 100 pF 22 k(1) 4 MHz(3) 470 100 nF
synthesizer trap control loop filter
VP = 5 V synthesizer downconverter loop filter(4)
RLFSYN2 CLFSYN2
analog ground n.c.
22 pF
i.c.
22 pF
n.c. 41 40 39 38 37 36 n.c.
CAF2
48 1
47
46
45
44
43
42
AGC input for DIF (from channel decoder)
n.c. SIF/DIF 1
51
2
35
1:1
5
3
34
1.5 nF
2 3
4
CIFAGC
4
33
2 V CVBS output BVS
5
470 nF
32
VIF/SIF/DIF
1
51
1:1
5
6
31
AUD (b) ZIF Q or 1st DIF (a)
CAF1
TDA9898
2 3 4
CCTAGC
7
30
8
100 nF
29
VIF/SIF/DIF
1
51
1:1
5
9
28
470 nF
2 3
4
10
27
(b) digital LIF or ZIF I or analog 2nd sound IF (a)
TOP potentiometer for RSSI and positive modulation MPP1 +5 V
2.7 k
11
22 k
26
12 13 only for port function 14 15 16 MPP2
Cpar 220 nF Cs Cde-em 4.7 nF
25 17 18 19 20 21 22 digital ground ADRSEL 23 24
330
FM PLL loop filter(5)
Rs 100 100
VIF loop filter
output to sound BPF
FM input from sound BPF
external FM input
SDA
SCL
008aaa045
(1) Connect resistor if external reference signal is not used. (2) Connect resistor if crystal is not used. (3) Use of crystal is optional. (4) Application depends on synthesizer frequency; see Table 57. (5) See Table 54.
Fig 50. Test circuit of TDA9898
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
93 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
tuner AGC output
4 MHz reference input
3.3 k(2)
synthesizer trap control loop filter
CTAGC 100 nF
CFREF 100 pF
22 k(1)
4 MHz(3)
470 100 nF
VP = 5 V synthesizer downconverter loop filter(4)
RLFSYN2 CLFSYN2
analog ground n.c.
22 pF
i.c.
22 pF
n.c. 41 40 39 38 37 36 n.c.
CAF2
48 1
47
46
45
44
43
42
AGC input for DIF (from channel decoder)
n.c. SIF/DIF 1
51
2
35
1:1
5
3
34
1.5 nF
2 3
4
4 n.c.
33
2 V CVBS output BVS
5
32
VIF/SIF/DIF
1
51
1:1
5
6
31
AUD (b) ZIF Q or 1st DIF (a)
CAF1
TDA9897
2 3 4
CCTAGC
7
30
8
100 nF
29
VIF/SIF/DIF
1
51
1:1
5
9
28
470 nF
2 3
4
10
27
(b) digital LIF or ZIF I or analog 2nd sound IF (a)
TOP potentiometer for RSSI and IF based tuner AGC MPP1 +5 V
2.7 k
11
22 k
26
12 13 only for port function 14 15 16 MPP2
Cpar 220 nF Cs Cde-em 4.7 nF
25 17 18 19 20 21 22 digital ground ADRSEL 23 24
330
FM PLL loop filter(5)
Rs 100 100
VIF loop filter
output to sound BPF
FM input from sound BPF
external FM input
SDA
SCL
008aaa044
(1) Connect resistor if external reference signal is not used. (2) Connect resistor if crystal is not used. (3) Use of crystal is optional. (4) Application depends on synthesizer frequency; see Table 57. (5) See Table 54.
Fig 51. Test circuit of TDA9897
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
94 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
15. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 52. Package outline SOT313-2 (LQFP48)
TDA9897_TDA9898_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
95 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1 index area A E A1 c
detail X
e1 e 13 L 12 25 e
1/2 e
C b 24 vMCAB wMC y1 C y
Eh
1/2 e
e2
1 terminal 1 index area 48 Dh 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 7.1 6.9 Dh 5.25 4.95 E (1) 7.1 6.9 Eh 5.25 4.95 e 0.5 37
36
X 2.5 scale e1 5.5 e2 5.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 5 mm
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-18
Fig 53. Package outline SOT619-1 (HVQFN48)
TDA9897_TDA9898_3 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
96 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
16. Soldering
16.1 Introduction
There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
16.2 Through-hole mount packages
16.2.1 Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
16.2.2 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
16.3 Surface mount packages
16.3.1 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 54) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 58 and 59
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
97 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 350 220 220
Table 58.
Package thickness (mm)
< 2.5 2.5 Table 59.
235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350
Package thickness (mm)
350 to 2000 260 250 245
> 2000 260 245 245
< 1.6 1.6 to 2.5 > 2.5
260 260 250
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 54.
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 54. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16.3.2 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
98 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
16.3.3 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
16.4 Package related soldering information
Table 60. Mounting Through-hole mount Through-hole-surface mount Suitability of IC packages for wave, reflow and dipping soldering methods Package[1] CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[4] Soldering method Wave suitable suitable[3] not suitable Reflow[2] - - not suitable Dipping - suitable -
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
99 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 60. Mounting
Suitability of IC packages for wave, reflow and dipping soldering methods ...continued Package[1] HTSSON..T[5], Soldering method Wave Reflow[2] suitable Dipping -
Surface mount
not suitable BGA, LBGA, LFBGA, SQFP, SSOP..T[5], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[7], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[10], WQCCN..L[10] not suitable[6]
suitable
-
suitable not not recommended[7][8] recommended[9]
suitable suitable suitable not suitable
- - - -
not suitable
[1] [2]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. Hot bar soldering or manual soldering is suitable for PMFP packages. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[3] [4] [5]
[6]
[7] [8] [9]
[10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request.
17. Abbreviations
Table 61. Acronym ADC AFC AGC ATV BP CW DAC DC
TDA9897_TDA9898_3
Abbreviations Description Analog-to-Digital Converter Automatic Frequency Control Automatic Gain Control Analog TV Band-Pass Continuous Wave Digital-to-Analog Converter Direct Current
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
100 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
Table 61. Acronym DIF DSP DTV DVB ESD FPLL IC IF LCD LIF MAD NICAM PLL POR QSS RIF RSSI SAW SC SIF TAGC TOP VCO VIF VITS ZIF
Abbreviations ...continued Description Digital Intermediate Frequency Digital Signal Processor Digital TV Digital Video Broadcast ElectroStatic Discharge Frequency Phase-Locked Loop Integrated Circuit Intermediate Frequency Liquid Crystal Display Low Intermediate Frequency Module Address Near Instantaneous Companded Audio Multiplex Phase-Locked Loop Power-On Reset Quasi Split Sound Radio Intermediate Frequency Received Signal Strength Indication Surface Acoustic Wave Sound Carrier Sound Intermediate Frequency Tuner Automatic Gain Control TakeOver Point Voltage-Controlled Oscillator Vision Intermediate Frequency Vertical Interval Test Signal Zero Intermediate Frequency
18. Revision history
Table 62. Revision history Release date 20080111 Data sheet status Product data sheet Product data sheet Product data sheet Change notice Supersedes TDA9897_TDA9898_2 TDA9897_TDA9898_1 Document ID TDA9897_TDA9898_3 Modifications: TDA9897_TDA9898_2 TDA9897_TDA9898_1
*
Additional specification of features for V2/S1 version
20070411 20060922
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
101 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TDA9897_TDA9898_3
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 03 -- 11 January 2008
102 of 103
NXP Semiconductors
TDA9897; TDA9898
Multistandard hybrid IF processing
21. Contents
1 2 2.1 2.2 2.3 2.4 2.5 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.8 8.9 8.10 9 9.1 9.2 9.2.1 9.2.2 10 11 12 12.1 12.2 13 14 15 16 16.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Analog TV processing. . . . . . . . . . . . . . . . . . . . 1 Digital TV processing . . . . . . . . . . . . . . . . . . . . 2 Dual mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 FM radio mode . . . . . . . . . . . . . . . . . . . . . . . . . 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Quick reference data . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pinning information . . . . . . . . . . . . . . . . . . . . . 12 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional description . . . . . . . . . . . . . . . . . . 14 IF input switch. . . . . . . . . . . . . . . . . . . . . . . . . 14 VIF demodulator . . . . . . . . . . . . . . . . . . . . . . . 15 VIF AGC and tuner AGC. . . . . . . . . . . . . . . . . 15 Mode selection of VIF AGC . . . . . . . . . . . . . . 15 VIF AGC monitor . . . . . . . . . . . . . . . . . . . . . . 15 Tuner AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DIF/SIF FM and AM sound AGC . . . . . . . . . . 16 Frequency phase-locked loop for VIF . . . . . . . 16 DIF/SIF converter stage . . . . . . . . . . . . . . . . . 16 Mono sound demodulator . . . . . . . . . . . . . . . . 17 Narrow-band FM PLL demodulation. . . . . . . . 17 AM sound demodulation . . . . . . . . . . . . . . . . . 17 Audio amplifier . . . . . . . . . . . . . . . . . . . . . . . . 17 Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C-bus transceiver and slave address . . . . . . 18 I2C-bus control . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Subaddress. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Description of data bytes . . . . . . . . . . . . . . . . 24 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal characteristics. . . . . . . . . . . . . . . . . . 37 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 38 Analog TV signal processing . . . . . . . . . . . . . 38 Digital TV signal processing . . . . . . . . . . . . . . 76 Application information. . . . . . . . . . . . . . . . . . 90 Test information . . . . . . . . . . . . . . . . . . . . . . . . 93 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 95 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 97 16.2 16.2.1 16.2.2 16.3 16.3.1 16.3.2 16.3.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Through-hole mount packages . . . . . . . . . . . 97 Soldering by dipping or by solder wave . . . . . 97 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 97 Surface mount packages . . . . . . . . . . . . . . . . 97 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 97 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 98 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 99 Package related soldering information . . . . . . 99 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . 101 Legal information . . . . . . . . . . . . . . . . . . . . . 102 Data sheet status . . . . . . . . . . . . . . . . . . . . . 102 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . 102 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 102 Contact information . . . . . . . . . . . . . . . . . . . 102 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 January 2008 Document identifier: TDA9897_TDA9898_3

▲Up To Search▲

Price & Availability of TDA9898HL

	To Download TDA9898HL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .